Datasheet
SN65HVDA1040A-Q1
SLLS995C –FEBRUARY 2010– REVISED FEBRUARY 2011
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THERMAL CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
THERMAL METRIC
(1)
TEST CONDITIONS MIN TYP MAX UNIT
THERMAL METRIC - SOIC 'D' PACKAGE
12.1-D Low-K thermal resistance
(3)
140
Junction-to-air thermal
θ
JA
resistance
(2)
12.2-D High-K thermal resistance
(4)
112
Junction-to-board thermal
12.3-D θ
JB
50
resistance
(5)
Junction-to-case (top) thermal
12.4-D θ
JC(TOP)
56
resistance
(6)
°C/W
Junction-to-case (bottom)
12.5-D θ
JC(BOTTOM)
NA
thermal resistance
(7)
Junction-to-top
12.6-D Ψ
JT
13
characterization parameter
(8)
Junction-to-board
12.7-D Ψ
JB
55
characterization parameter
(9)
THERMAL METRIC - VSON 'DSJ' PACKAGE
12.1-DSJ Low-K thermal resistance
(3)
290
Junction-to-air thermal
θ
JA
resistance
(2)
12.2-DSJ High-K thermal resistance
(4)
52
Junction-to-board thermal
12.3-DSJ θ
JB
14
resistance
(5)
Junction-to-case (top) thermal
12.4-DSJ θ
JC(TOP)
56
resistance
(6)
°C/W
Junction-to-case (bottom)
12.5-DSJ θ
JC(BOTTOM)
4.5
thermal resistance
(7)
Junction-to-top
12.6-DSJ Ψ
JT
6
characterization parameter
(8)
Junction-to-board
12.7-DSJ Ψ
JB
19
characterization parameter
(9)
AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN
V
CC
= 5 V, T
J
= 27°C, R
L
= 60 Ω, STB at 0 V,
12.5 Input to TXD at 500 kHz, 50% duty cycle 112
square wave, C
L
at RXD = 15 pF
P
D
Average power dissipation mW
V
CC
= 5.5 V, T
J
= 130°C, R
L
= 45 Ω, STB at
0 V,
12.6 170
Input to TXD at 500 kHz, 50% duty cycle
square wave, C
L
at RXD = 15 pF
Thermal shutdown
12.7 185 °C
temperature
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction temperature (T
J
) is calculated using the following T
J
= T
A
+ (P
D
× θ
JA
). θ
JA
is PCB dependent, both JEDEC-standard Low-K
and High-K values are given as reference points to standardized reference boards.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, Low-K board, as
specified in JESD51-3, in an environment described in JESD51-2a.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(8) The junction-to-top characterization parameter, Ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-board characterization parameter, Ψ
JB
estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
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