Datasheet

SN65HVD96
SLLSE35B – JUNE 2010–REVISED NOVEMBER 2011 www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE UNIT
Supply voltage, V
CC
–0.5 to 6 V
Voltage range at A or B –35 to 40 V
Voltage range at logic pins (D, DE, RE) –0.3 to V
CC
+0.3 V
Voltage input range, transient pulse, A and B, through 100Ω ±25 V
Voltage input transient pulse, A and B, per ISO 7637 ±200 V
Differential voltage, V
A
– V
B
–75 to +75 V
Electro-static discharge per JEDEC Std. 22 A114, A and B pins, Human Body Model ±12 kV
Electro-static discharge per JEDEC Std. 22 A114, all pins, Human Body Model ±5 kV
Electro-static discharge per JEDEC Std. 22 C101, all pins, Charged Device Model ±2 kV
Electro-static discharge per JEDEC Std. 22 A115, all pins, Machine Model ±200 V
Receiver output current ±20 mA
Junction temperature, T
J
170 °C
Continuous total power dissipation (see Dissipation Rating Table)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
SN65HVD96
THERMAL METRIC
(1)
UNITS
8 PINS SOIC
θ
JA
Junction-to-ambient thermal resistance
(2)
124.5
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
55.9
θ
JB
Junction-to-board thermal resistance
(4)
50.2
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
4.9
ψ
JB
Junction-to-board characterization parameter
(6)
46.0
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a
TEST CONDITIONS
VCC = 5.25 V, TJ = 150°C, RL = 300 Ω, CL = 50 pF (driver),
188
CL = 15 pF (receiver), unterminated
(8)
P
d
Power Dissipation
VCC = 5.25 V, TJ = 150°C, RL = 100 Ω, CL = 50 pF (driver),
251 mW
CL = 15 pF (receiver), RS-422 load
(8)
VCC = 5.25 V, TJ = 150°C, RL = 54 Ω, CL = 50 pF (driver),
319
CL = 15 pF (receiver), RS-485 load
(8)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(8) Driver and receiver enabled, 50% duty cycle square-wave signal at 5 Mbps.
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