Datasheet
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
HVD30, HVD33 4 10 18
Propagation delay time, low-to-high-level
t
PLH
HVD31, HVD34 25 38 65 ns
output
HVD32, HVD35 120 175 305
HVD30, HVD33 4 9 18
Propagation delay time, high-to-low-level
t
PHL
HVD31, HVD34 25 38 65 ns
output
HVD32, HVD35 120 175 305
HVD30, HVD33 2.5 5 12
R
L
= 54 Ω, C
L
= 50 pF,
t
r
Differential output signal rise time HVD31, HVD34 20 37 60 ns
See Figure 5
HVD32, HVD35 120 185 300
HVD30, HVD33 2.5 5 12
t
f
Differential output signal fall time HVD31, HVD34 20 35 60 ns
HVD32, HVD35 120 180 300
HVD30, HVD33 0.6
t
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) HVD31, HVD34 2.0 ns
HVD32, HVD35 5.1
HVD33 45
Propagation delay time,
t
PZH1
HVD34 235 ns
high-impedance-to-high-level output
R
L
= 110 Ω, RE at 0 V,
HVD35 490
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
HVD33 25
See Figure 6
Propagation delay time,
t
PHZ
HVD34 65 ns
high-level-to-high-impedance output
HVD35 165
HVD33 35
Propagation delay time,
t
PZL1
HVD34 190 ns
high-impedance-to-low-level output
R
L
= 110 Ω, RE at 0 V,
HVD35 490
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
HVD33 30
See Figure 7
Propagation delay time,
t
PLZ
HVD34 120 ns
low-level-to-high-impedance output
HVD35 290
t
PZH1,
Driver enable delay with bus voltage offset V
O
= 2 V (Typ) 500 900 ns
t
PZL1
R
L
= 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
t
PZH2
Propagation delay time, standby-to-high-level output 4000 ns
D = 0 V and S1 = Z
See Figure 6
R
L
= 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
t
PZL2
Propagation delay time, standby-to-low-level output 4000 ns
D = 0 V and S1 = Y
See Figure 7
(1) All typical values are at 25°C and with a 3.3-V supply.
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