Datasheet

Input
Generator
50 Ω
V
O
S1
V
CC
3V
V
CC
1.5V 1.5V
t
PZL(1&2)
t
PLZ
2.3V
0.5V
0V
V
OL
V
I
V
O
R
L
=110 Ω
± 1%
C
L
=50pF ±20%
D
Y
Z
DE
V
I
DS1
3VZ
0V Y
Generator:PRR=50kHz,50%DutyCycle,t
r
<6ns,t
f
<6ns,Z
0
=50 W
C
L
IncludesFixtureandInstrumentationCapacitance
V
ID
V
A
V
B
I
O
A
B
I
B
V
O
R
RE
I
A
V
IC
V
A
+V
B
2
I
I
V
I
Input
Generator
50 Ω
Generator:PRR=500kHz,50%DutyCycle,t
r
<6ns,t
f
<6ns,Z
o
=50 Ω
V
O
1.5V
0V
1.5V 1.5V
3V
V
OH
V
OL
1.5V
10%
1.5V
t
PLH
t
PHL
t
r
t
f
90%
V
I
V
O
C
L
=15pF
±20%
C IncludesFixtureandInstrumentationCapacitance
L
A
B
RE
V
I
R
0V
90%
10%
B
A
R
V
O
50 W
V
I
Input
Generator
C
L
=15 pF
±20%
C
L
IncludesFixtureand
InstrumentationCapacitance
RE
S1
1k W ±1%
A
B
V
CC
V
I
t
PZH(1&2)
3V
1.5V
1.5V
t
PHZ
0V
V
O
1.5V
~0V
V
OH
0.5V
1.5V
0V
Generator:PRR=50kHz,50%DutyCycle,t
r
<6ns,t
f
<6ns,Z
0
=50 W
SN65HVD30 – SN65HVD35
www.ti.com SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 8. Receiver Voltage and Current Definitions
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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