Datasheet

SN65HVD3082E, SN75HVD3082E
SN65HVD3085E, SH65HVD3088E
SLLS562G –AUGUST 2009–REVISED MAY 2009 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
Supply voltage range, V
CC
–0.5 V to 7 V
Voltage range at A or B –9 V to 14 V
Voltage range at any logic pin –0.3 V to V
CC
+ 0.3 V
Receiver output current –24 mA to 24 mA
Voltage input, transient pulse, A and B, through 100 Ω. See Figure 13 –50 to 50 V
Junction Temperature, T
J
170°C
Continuous total power dissipation See the Package Dissipation Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
JEDEC BOARD T
A
< 25°C DERATING FACTOR
(1)
T
A
= 70°C T
A
= 85°C
PACKAGE
ABOVE T
A
= 25°C POWER RATING POWER RATING
MODEL POWER RATING
Low k
(2)
507 mW 4.82 mW/°C 289 mW 217 mW
D
High k
(3)
824 mW 7.85 mW/°C 471 mW 353 mW
P Low k
(2)
686 mW 6.53 mW/°C 392 mW 294 mW
Low k
(2)
394 mW 3.76 mW/°C 255 mW 169 mW
DGK
High k
(3)
583 mW 5.55 mW/°C 333 mW 250 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the low-k thermal metric definitions of EIA/JESD51-3
(3) In accordance with the high-k thermal metric definitions of EIA/JESD51-7
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