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SN65HVD257 EVM Setup and Operation for Redundant (Parallel Networks)

3 SN65HVD257 EVM Setup and Operation for Redundant (Parallel Networks)

This section describes the setup and operation of the EVM for parameter performance evaluation.

3.1 Overview and Basic Operation Settings

3.1.1 V

Power Supply (TB1 or TP12 or JMP1)

The basic setup of the EVM requires a single power supply to evaluate transceiver and network design

performance. Supply V

on TB1, JMP1 header or via the V

and GND test point loops. The supplie

powerd must meet the required specification of V

for the transceiver being tested. LED D3 indicates V

3.1.2 Main Supply and IO Header (JMP1)

All key IO and supply GND functions are brought to this header. It may be used to interface test

equipment, or a short cable can be made to connect to an existing customer application board or MCU or

DSP EVM board.

Table 2. Main Supply and IO Header (JMP1) Connections

Pin Connection Description

1 S1 Pin 5 of Transceiver 1. Used for Mode control.

2 FLT1 Pin 8 of Transceiver 1. Indicates fault with transceiver 1.

3 GND GND

4 TXD Pin 1 of Transceiver 1 and 2 (signal TXDprime). TXD (Transmit Data)

5 GND GND

6 RXD Pin 4 of Transceiver 1 and 2 combined via AND gate U2 (signal RXDprime). RXD (Receive Data)

7 GND GND

8 VCC Pin 3 of Transceiver. V

9 S2 Pin 5 of Transceiver 2. Used for Mode control.

10 FLT2 Pin 8 of Transceiver 2. Indicates fault with transceiver 2.

11 GND GND

12 FLT3 FAULT3: Open fault indicator. RXD (Pin 4) outputs of transceiver 1 and 2 combined via XOR gate U6 with

filter (signal FAULT3). Indicates bus open faults.

3.1.3 TXD Input (JMP1)

The TXD input on JMP1 is connected via signal TXDprime to the TXD pin (pin 1) of both transceivers for

redundant (parallel) transmission on both buses. Individually this signal may be observed at the

transceiver pin via TP5 (transceiver 1) and TP18 (transceiver 2). The signal path TXDprime to the JMP1

header is pre-installed with a 0Ω series resistor, R10 and R34.

3.1.4 TXD Output (JMP1)

The RXD (combined) output of the transceivers via the AND gate for redundant (parallel) buses is JMP1.

Individually the RXD signals may be seen at the transceiver pin via TP8 (transceiver 1) and TP21

(transceiver 2). The combined RXD (RXDprime) signal path to the JMP1 header is pre-installed with a 0Ω

series resistor, R20 from the output of the AND gate U2.

3.1.5 S Pin (Mode Selection, pin 8) (JMP1, JMP2, JMP8, TP6 and TP19)

Pin 8 of the transceiver is the mode control pin of the device. Pin 8 of the devices is routed to JMP1,

JMP2 and JMP8.

SLLU172–August 2012 SN65HVD257 CAN EVM: Functional Safety and Redundant CAN Network

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