Datasheet

SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com SLLSEA2C –DECEMBER 2011–REVISED SEPTEMBER 2013
5 V V
CC
with FAULT Open-Drain Output Device (SN65HVD257):
This device has a FAULT output pin (open-drain). FAULT must be pulled up to V
CC
or I/O supply level via an
external resistor.
APPLICATION NOTE: Because the FAULT output pin is open-drain, it actively pulls down when there is no
fault, and becomes high-impedance when a fault condition is detected. An external pullup resistor to the V
CC
or I/O supply of the system must be used to pull the pin high to indicate a fault to the host microprocessor.
The open-drain architecture makes the fault pin compatible with 3.3 V and 5 V I/O-level systems. The pullup
current, selected by the pullup resistance value, should be as low as possible while achieving the desired
voltage level output in the system with margin against noise.
PROTECTION FEATURES
TXD Dominant Timeout (DTO)
During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the
transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the timeout period t
TXD_DTO
. The DTO circuit timer starts on a falling edge on TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal is seen on TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect
the CAN bus, and the bus pins are biased to recessive level during a TXD dominant timeout.
APPLICATION NOTE: The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by
an error frame. This, along with the t
TXD_DTO
minimum, limits the minimum data rate. Calculate the minimum
transmitted data rate by: Minimum Data Rate = 11 / t
TXD_DTO
.
RXD Dominant Timeout (SN65HVD257)
The SN65HVD257 device has a RXD dominant timeout (RXD DTO) circuit that prevents a bus stuck dominant
fault from permanently driving the RXD output dominant (low) when the bus is held dominant longer than the
timeout period t
RXD_DTO
. The RXD DTO timer starts on a falling edge on RXD (bus going dominant). If no rising
edge (bus returning recessive) is seen before the timeout constant of the circuit expires (t
RXD_DTO
), the RXD pin
returns high (recessive). The RXD output is re-activated to mirror the bus receiver output when a recessive signal
is seen on the bus, clearing the RXD dominant timeout. The CAN bus pins are biased to the recessive level
during a RXD DTO.
APPLICATION NOTE: The minimum dominant RXD time allowed by the RXD DTO limits the minimum
possible received data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits for the worst case transmission, where five successive dominant bits are followed immediately
by an error frame. This, along with the t
RXD_DTO
minimum, limits the minimum data rate. The minimum
received data rate may be calculated by: Minimum Data Rate = 11 / t
RXD_DTO
.
Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device.
APPLICATION NOTE: During thermal shutdown the CAN bus drivers turn off; thus no transmission is
possible from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown,
and the receiver to RXD path remains operational.
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Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257