Datasheet

SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2C –DECEMBER 2011–REVISED SEPTEMBER 2013 www.ti.com
Unpowered Device
The device is designed to be an 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus pins
(CANH, CANL) have extremely low leakage currents when the device is unpowered so they will not load down
the bus. This is critical if some nodes of the network will be unpowered while the rest of the of network remains in
operation. The logic pins also have extremely low leakage currents when the device is unpowered to avoid
loading down other circuits that may remain powered.
Floating Pins
The device has internal pull ups and pull downs on critical pins to place the device into known states if the pins
float. The TXD pin is pulled up to V
CC
to force a recessive input level if the pin floats. The S pin is pulled down to
GND to force the device into normal mode if the pin floats.
CAN Bus Short Circuit Current Limiting
The device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
APPLICATION NOTE: The short circuit current of the bus depends on the ratio of recessive to dominant bits
and their respective short circuit currents. The average short circuit current may be calculated with the
following formula:
I
OS(AVG)
= %Transmit × [(%REC_Bits × I
OS(SS)_REC
) + (%DOM_Bits × I
OS(SS)_DOM
)] + [%Receive × I
OS(SS)_REC
]
Where
• I
OS(AVG)
is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• I
OS(SS)_REC
is the recessive steady state short circuit current
• I
OS(SS)_DOM
is the dominant steady state short circuit current
APPLICATION NOTE: Consider the short circuit current and possible fault cases of the network when sizing
the power ratings of the termination resistance and other network components.
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