Datasheet

SN65HVD255
SN65HVD256, SN65HVD257
www.ti.com SLLSEA2C –DECEMBER 2011–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted). SN65HVD256 device V
RXD
= V
CC
.
PARAMETER TEST CONDITIONS / COMMENT MIN TYP
(1)
MAX UNIT
13.0 FAULT Pin (Fault Output), SN65HVD257 only
13.1 I
CH
Output current high level FAULT = V
CC
, See Figure 9 –10 10 µA
13.2 I
CL
Output current low level FAULT = 0.4 V, See Figure 9 5 12 mA
THERMAL CHARACTERISTICS
13.0 THERMAL METRIC
(1)
TEST CONDITIONS TYP UNIT
13.1 θ
JA
Junction-to-air thermal resistance High-K thermal resistance
(2)
107.5
13.2 θ
JB
Junction-to-board thermal resistance
(3)
48.9
13.3 θ
JC(TOP)
Junction-to-case (top) thermal resistance
(4)
56.7 °C/W
13.4 Ψ
JT
Junction-to-top characterization parameter
(5)
12.1
13.5 Ψ
JB
Junction-to-board characterization parameter
(6)
48.2
V
CC
= 5 V, V
RXD
= 5 V, T
J
= 27°C, R
L
= 60 Ω, S at
0 V, Input to TXD at 250 kHz, 25% duty cycle
13.6 square wave, C
L_RXD
= 15 pF. Typical CAN 115
operating conditions at 500kbps with 25%
transmission (dominant) rate.
P
D
Average power dissipation mW
V
CC
= 5.5 V, V
RXD
= 5.5 V, T
J
= 150°C, R
L
= 50 Ω,
S at 0 V, Input to TXD at 500 kHz, 50% duty cycle
13.7 square wave, C
L_RXD
= 15 pF. Typical high load 268
CAN operating conditions at 1mbps with 50%
transmission (dominant) rate and loaded network.
13.8 Thermal shutdown temperature 170 °C
13.9 Thermal shutdown hysteresis 5 °C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) he junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, Ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, Ψ
JB
estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
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