Datasheet

SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2C –DECEMBER 2011–REVISED SEPTEMBER 2013 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted). SN65HVD256 device V
RXD
= V
CC
.
PARAMETER TEST CONDITIONS / COMMENT MIN TYP
(1)
MAX UNIT
10.0 DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, HIGH TXD to
10.1 t
pHR
50 70
Driver Recessive
Propagation delay time, LOW TXD to
10.2 t
pLD
40 70
See Figure 10, S = 0 V, R
L
= 60 Ω,
Driver Dominant
ns
C
L
= 100 pF, R
CM
= open
10.3 t
sk(p)
Pulse skew (|t
pHR
- t
pLD
|) 10
10.4 t
R
Differential output signal rise time 10 30
10.5 t
F
Differential output signal fall time 17 30
Differential output signal rise time,
10.6 t
R(10k)
35
R
L
= 10 kΩ
See Figure 10, S = 0 V, R
L
= 10 kΩ,
ns
CL
= 10 pF, R
CM
= open
Differential output signal fall time,
10.7 t
F(10k)
100
R
L
= 10 kΩ
See Figure 14, R
L
= 60 Ω, C
L
=
10.8 t
TXD_DTO
Dominant timeout
(3)
1175 3700 µs
open
11.0 RECEIVER ELECTRICAL CHARACTERISTICS
Positive-going input threshold voltage,
11.1 V
IT+
900 mV
normal mode
See Figure 11, Table 3 and Table 6
Negative-going input threshold voltage,
11.2 V
IT–
500 mV
normal mode
11.3 V
HYS
Hysteresis voltage (V
IT+
- V
IT–
) 125 mV
Power-off (unpowered) bus input C
ANH
= C
ANL
= 5 V, V
CC
= 0 V, V
RXD
11.4 I
IOFF(LKG)
5.5 µA
leakage current = 0 V
Input capacitance to ground (CANH or TXD = V
CC
, V
RXD
= V
CC
, V
I
= 0.4 sin
11.5 C
I
25 pF
CANL) (4E6 π t) + 2.5 V
TXD = V
CC
, V
RXD
= V
CC
, V
I
= 0.4 sin
11.6 C
ID
Differential input capacitance 10 pF
(4E6 π t)
11.7 R
ID
Differential input resistance 30 80 kΩ
TXD = V
CC
= V
RXD
= 5 V, S = 0 V
11.8 R
IN
Input resistance (CANH or CANL) 15 40 kΩ
Input resistance matching:
V
(CANH)
= V
(CANL)
, –40°C ≤ T
A
≤
11.9 R
IN(M)
–3% 3%
85°C
[1 – R
IN(CANH)
/ R
IN(CANL)
] × 100%
12.0 RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, recessive input
12.1 t
pRH
70 90 ns
to high output
Propagation delay time, dominant input
12.2 t
pDL
70 90 ns
See Figure 11, C
L_RXD
= 15 pF
to low output
12.3 t
R
Output signal rise time 4 20 ns
12.4 t
F
Output signal fall time 4 20 ns
Receiver dominant time out
12.5 t
RXD_DTO
(4)
(SN65HVD257 only) See Figure 8, 1380 4200 µs
C
L_RXD
= 15 pF
(3) The TXD dominant timeout (t
TXD_DTO
) disables the driver of the transceiver once the TXD has been dominant longer than t
TXD_DTO
,
which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the t
TXD_DTO
minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t
TXD_DTO
= 11 bits / 1175 µs = 9.4 kbps.
(4) The RXD timeout (t
RXD_DTO
) disables the driver of the transceiver once the RXD has been dominant longer than t
RXD_DTO
, which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after RXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on RXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t
RXD_DTO
minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t
RXD_DTO
= 11 bits / 1380 µs = 8 kbps.
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