Datasheet

SN55HVD251
SN65HVD251
www.ti.com SLLS545E –NOVEMBER 2002–REVISED MARCH 2010
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT+
Positive-going input threshold voltage 750 900
V
IT-
Negative-going input threshold voltage Rs at 0 V, (See Table 1) 500 650 mV
V
hys
Hysteresis voltage (V
IT+
- V
IT-
) 100
V
OH
High-level output voltage Figure 6, I
O
= -4mA 0.8 V
CC
V
V
OL
Low-level output voltage Figure 6, I
O
= 4mA 0.2 V
CC
V
CANH or CANL at 12 V 600
CANH or CANL at 12 V,
Other bus
715
V
CC
at 0 V
pin at 0 V,
I
I
Bus input current µA
Rs at 0 V, D
CANH or CANL at -7 V -460
at 0.7 V
CC
CANH or CANL at -7 V,
-340
V
CC
at 0 V
Pin-to-ground, V
I
= 0.4 sin (4E6pt) + 0.5 pF
C
I
Input capacitance, (CANH or CANL) 20
V, D at 0.7 V
CC
Pin-to-pin, V
I
= 0.4 sin (4E6pt) + 0.5 V, D pF
C
ID
Differential input capacitance 10
at 0.7 V
CC
R
ID
Differential input resistance D at 0.7 V
CC
, Rs at 0 V 40 100 kΩ
R
IN
Input resistance, (CANH or CANL) D at 0.7 V
CC
, Rs at 0 V 20 50 kΩ
Receiver noise rejection See Figure 13
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
pLH
Propagation delay time, low-to-high-level output 35 50
t
pHL
Propagation delay time, high-to-low-level output 35 50
t
sk(p)
Pulse skew (|t
pHL
- t
pLH
|) Figure 6 20
ns
t
r
Output signal rise time 2 4
t
f
Output signal fall time 2 4
t
p(sb)
Propagation delay time in standby Figure 12, Rs at V
CC
500
VREF-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
-5 µA < I
O
< 5 µA 0.45 V
CC
0.55 V
CC
V
O
Reference output voltage V
-50 µA < I
O
< 50 µA 0.4 V
CC
0.6 V
CC
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Figure 10, Rs at 0 V 60 100
Total loop delay, driver input to receiver
t
loop1
Figure 10, Rs with 10 kΩ to ground 100 150 ns
output, recessive to dominant
Figure 10, Rs with 100 kΩ to ground 440 800
Figure 10, Rs at 0 V 115 150
Total loop delay, driver input to receiver
t
loop2
Figure 10, Rs with 10 kΩ to ground 235 290 ns
output, dominant to recessive
Figure 10, Rs with 100 kΩ to ground 1070 1450
Total loop delay, driver input to receiver
t
loop2
Figure 10, Rs at 0 V, V
CC
from 4.5 V to 5.1 V, 105 145 ns
output, dominant to recessive
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN55HVD251 SN65HVD251