Datasheet

SN55HVD251
SN65HVD251
SLLS545E –NOVEMBER 2002–REVISED MARCH 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE RANGE MARKED AS
SN65HVD251D 8-pin Small Outline Integrated Circuit (SOIC) -40°C to 125°C VP251
SN65HVD251P 8-pin Dual Inline Package (DIP) -40°C to 125°C 65HVD251
SN55HVD251DRJ 8-pin Small Outline No-Lead (SON) -55°C to 125°C SN55HVD251
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Values
Supply voltage range, V
CC
-0.3 V to 7 V
Voltage range at any bus terminal (CANH or CANL) -36 V to 36 V
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b CANH, CANL ±200 V
Input voltage range, V
I
(D, Rs, or R) -0.3 V to V
CC
+ 0.5
Receiver output current, I
O
–10 mA to 10 mA
CANH, CANL and GND 14 kV
Human Body Model
(3)
Electrostatic discharge All pins 6 kV
Charged-Device Model
(4)
All pins 1 kV
Electrical fast transient/burst IEC 61000-4-4, Classification B CANH, CANL ±3 kV
(see the Package
Continuous total power dissipation
Dissipation Ratings Table)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
CIRCUIT BOARD T
A
= 25°C DERATING FACTOR
(1)
T
A
= 85°C POWER T
A
= 125°C POWER
PACKAGE
MODEL POWER RATING ABOVE T
A
= 25°C RATING RATING
Low-K
(2)
576 mW 4.8 mW/°C 288 mW 96 mW
SOIC (D)
High-K
(3)
924 mW 7.7 mW/°C 462 mW 154 mW
Low-K
(2)
888 mW 7.4 mW/°C 444 mW 148 mW
PDIP (P)
High-K
(3)
1212 mW 10.1 mW/°C 606 mW 202 mW
Low-K
(2)
403 mW 4.03 mW/°C 262 mW 100 mW
High-K
1081 mW 10.8 mW/°C 703 mW 270 mW
SON (DRJ) (no Vias)
(3)
High-K
2793 mW 27.9 mW/°C 1815 mW 698 mW
(with Vias)
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
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