Datasheet

SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002– REVISED MAY 2010 www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high level output HVD20, HVD23 16 35 ns
See Figure 11
HVD21, HVD22,
t
PHL
Propagation delay time high-to low level output 25 50
HVD24
tr
Receiver output rise time
See Figure 11 2 4 ns
t
f
Receiver output fall time
t
PZH
Receiver output enable time to high level 90 120 ns
See Figure 12
t
PHZ
Receiver output disable time from high level 16 35
t
PZL
Receiver output enable time to low level 90 120 ns
See Figure 13
t
PLZ
Receiver output disable time from low level 16 35
t
r(standby)
Time from an active receiver output to standby 2 µs
See Figure 14, DE at 0 V
t
r(wake)
Wake-up time from standby to an active receiver output 8
t
sk(p)
Pulse skew |t
PLH
– t
PHL
| 5
t
p(set)
Delay time, bus fail to failsafe set 250 350 µs
See Figure 15, pulse rate = 1 kHz
t
p(reset)
Delay time, bus recovery to failsafe reset 50 ns
RECEIVER EQUALIZATION CHARACTERISTICS
(1)
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
0 m HVD23 2 ns
HVD20 6
100 m ns
HVD23 3
25 Mbps HVD20 15
150 m ns
HVD23 4
HVD20 27
200 m ns
HVD23 8
HVD20 22
200 m ns
HVD23 8
Peudo-random NRZ code with a bit
HVD20 34
10 Mbps 250 m ns
Peak-to-peak pattern length of 2
16
– 1, Beldon
t
j(pp)
HVD23 15
eye-pattern jitter 3105A cable,
HVD20 49
See Figure 27
300 m ns
HVD23 27
HVD21 128
5 Mbps 500 m ns
HVD24 18
HVD20 93
HVD21 103
3 Mbps 500 m ns
HVD23 90
HVD24 16
HVD21 216
1 Mbps 1000 m ns
HVD24 62
(1) The HVD20 and HVD21 do not have receiver equalization, but are specified for comparison.
(2) All typical values are at V
CC
= 5 V, and temperature = 25°C.
6 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24