Datasheet

SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002– REVISED MAY 2010 www.ti.com
TEST MODE DRIVER DISABLE
If the input signal to the D pin is such that:
1. the signal has signaling rate above 4 Mbps (for the ‘HVD21 and ‘HVD24)
2. the signal has signaling rate above 6 Mbps (for the ‘HVD20 and ‘HVD23)
3. the signal has average amplitude between 1.2 V and 1.6 V (1.4 V ±200 mV)
4. the average signal amplitude remains in this range for 100 µsec or longer,
then the driver may activate a test-mode during which the driver outputs are temporarily disabled. This can cause
loss of transmission of data during the period that the device is in the test-mode. The driver will be re-enabled
and resume normal operation whenever the above conditions are not true. The device is not damaged by this
test mode.
Although rare, there are combinations of specific voltage levels and input data patterns within the operating
conditions of the HVD2x family which may lead to a temporary state where the driver outputs are disabled for a
period of time.
Observations:
1. The conditions for inadvertently entering the test mode are dependent on the levels, duration, and duty cycle
of the logic signal input to the D pin. Operating input levels are specified as greater than 2 V for a logic HIGH
input, and less than 0.8V for a logic LOW input. Therefore, a valid steady-state logic input will not cause the
device to activate the test mode
2. Only input signals with frequency content above 2 MHz (4 Mbps) have a possibility of activating the test
mode. Therefore, this issue should not affect the normal operation of the HVD22 (500 kbps).
3. For operating signaling rates of 4 Mbps (or above), the conditions stated above must remain true over a
period of: 4 Mbps x 100 µsec = 400 bits. Therefore, a normal short message will not inadvertently activate
the test model
4. One example of an input signal which may cause the test mode to activate is a clock signal with frequency 3
MHz and 50% duty cycle (symmetric HIGH and LOW half-cycles) with logic HIGH levels of 2.4 V and logic
LOW levels of 0.4 V. This signal applied to the D pin as a driver input would meet the criteria listed above,
and might cause the test-mode to activate, which would disable the driver. Note that this example situation
might occur if the clock signal were generated by a microcontroller or logic chip with a 2.7 V-supply.
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24