Datasheet

SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002– REVISED MAY 2010 www.ti.com
INTEGRATED RECEIVER EQUALIZATION USING THE HVD24
Figure 29 illustrates the benefits of integrated receiver equalization as implemented in the HVD24 transceiver. In
this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was Belden
3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of nonreturn-to-zero
(NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle) shows the eye-pattern
of the differential voltage at the receiver inputs (after the cable attenuation). Channel 3 (bottom) shows the output
of the receiver.
Figure 29. HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24