Datasheet

B
A
6
7
R
2
1
RE
DE
D
3
4
Active
Filters
+
+
120mV
120mV
Timer
250 sm
(V
A
-V
B
):NotHigh
(V
A
-V
B
):NotLow
BusInput
Invalid
Slew
Rate
Control
STANDBY
-
-
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com SLLS552E –DECEMBER 2002–REVISED MAY 2010
APPLICATION INFORMATION
THEORY OF OPERATION
The HVD2x family of devices integrates a differential receiver and differential driver with additional features for
improved performance in electrically-noisy, long-cable, or other fault-intolerant applications.
The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps
reject spurious noise signals which would otherwise cause false changes in the receiver output state.
Slew rate limiting on the driver outputs (SN65HVD21, 22, and 24) reduces the high-frequency content of signal
edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and
the main bus line. Designers should consider the maximum signaling rate and cable length required for a specific
application, and choose the transceiver best matching those requirements.
When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When
DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D
input.s
When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state.
When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus
inputs on the A and B pins.
If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including
auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This reduces
power consumption to less than 5µW. When either enable input is asserted, the circuitry again becomes active.
In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to
implement an active receiver failsafe feature. These components determine whether the differential bus signal is
valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the
differential input remains within the transition range for more than 250 microseconds, the timer expires and set
the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output
reflects the valid bus state, and the timer is reset.
Figure 25. Function Block Diagram
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24