Datasheet
SN65HVD20, SN65HVD21
SN65HVD22, SN65HVD23, SN65HVD24
SLLS552E –DECEMBER 2002– REVISED MAY 2010
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THERMAL INFORMATION
SN65HVD2x
THERMAL METRIC
(1)
SOIC (D) PDIP (P) UNITS
8 PINS PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
78.1 52.5
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
56.5 57.6
θ
JB
Junction-to-board thermal resistance
(4)
50.4 38.6
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
4.1 19.1
ψ
JB
Junction-to-board characterization parameter
(6)
32.6 31.9
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
nA n/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
POWER DISSIPATION
PARAMETERS TEST CONDITIONS VALUE UNIT
HVD20 V
CC
= 5 V, T
J
= 25°C, 25 Mbps 295
R
L
= 54 Ω, C
L
= 50 pF (driver),
HVD21 5 Mbps 260
C
L
= 15 pF (receiver),
Typical HVD22 500 kbps 233 mW
50% Duty cycle square-wave signal,
Driver and receiver enabled
HVD23 25 Mbps 302
HVD24 5 Mbps 267
Device Power
dissipation, P
D
HVD20 V
CC
= 5.5 V, T
J
= 125°C, 25 Mbps 408
R
L
= 54 Ω, C
L
= 50 pF,
HVD21 5 Mbps 342
C
L
= 15 pF (receiver),
Worst case HVD22 500 kbps 300 mW
50% Duty cycle square-wave signal,
Driver and receiver enabled
HVD23 25 Mbps 417
HVD24 5 Mbps 352
Thermal shut down junction temperature, T
SD
170 °C
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Product Folder Link(s): SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24