Datasheet

SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS398A − APRIL 2002 − REVISED APRIL 2008
21
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APPLICATION INFORMATION
high-speed mode (continued)
1
1 Mbps
Driver Output
NRZ Data
Figure 30. Typical SN65HVD230Q High-Speed Mode Output Waveform Into a 60-Ω Load
slope-control mode
Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system
cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise
and fall slopes of the SN65HVD230Q and SN65HVD231Q driver outputs can be adjusted by connecting a
resistor from R
S
(pin 8) to ground or to a logic low voltage, as shown in Figure 31. The slope of the driver output
signal is proportional to the pin’s output current. This slope control is implemented with an external resistor value
of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew rate as displayed in
Figure 32. Typical driver output waveforms from a pulse input signal with and without slope control are displayed
in Figure 33. A pulse input is used rather than NRZ data to clearly display the actual slew rate.
TMS320LF2406
or
TMS320LF2407
IOPF6
1
2
3
4
8
7
6
5
D
GND
V
CC
R
CANH
CANL
Vref
10 kΩ
to
100 kΩ
R
S
SN65HVD230Q
Figure 31. Slope-Control or Standby Mode Connection to a DSP