Datasheet
SN65HVD21A
SLLSE36 –DECEMBER 2010
www.ti.com
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input clamp voltage I
I
= −18 mA –1.5 0.75 V
V
O
Open-circuit output voltage A or B, No load 0 V
CC
V
No load (open circuit) 3.3 4.2 V
CC
|V
OD(SS)
| Steady-state differential output voltage R
L
= 54 Ω, See Figure 1 1.8 2.5 V
With common-mode loading, See Figure 2 1.8
Change in steady-state differential
Δ|V
OD(SS)
| See Figure 1 and Figure 3 –0.1 0.1 V
output voltage between logic states
Steady-state common-mode output
V
OC(SS)
See Figure 1 2.1 2.5 2.9 V
voltage
Change in steady-state common-mode
∆V
OC(SS)
See Figure 1 and Figure 4 –0.1 0.1 V
output voltage, V
OC(H)
– V
OC(L)
Peak-to-peak common-mode output
V
OC(PP)
R
L
= 54 Ω, C
L
= 50 pF, See Figure 1 and Figure 4 0.35 V
voltage, V
OC(MAX)
– V
OC(MIN)
Differential output voltage over and
V
OD(RING)
R
L
= 54 Ω, C
L
= 50 pF, See Figure 5 10%
under shoot
I
I
Input current D, DE –100 100 µA
V
O
< = -7 V to 12 V, Other input = 0 V -100 125
Output current with power off.
I
O
µA
High impedance state output current.
V
O
< = -20 V to 25 V, Other input = 0 V -200 250
I
OS
Short-circuit output current V
O
= –20 V to 25 V, See Figure 9 –250 250 mA
C
OD
Differential output capacitance 20 pF
(1) All typical values are at V
CC
= 5 V and 25°C.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Differential output propagation delay, low-to-high R
L
= 54 Ω,
C
L
= 50 pF, 20 32 60 ns
t
PHL
Differential output propagation delay, high-to-low
See Figure 3
t
r
Differential output rise time R
L
= 54 Ω,
C
L
= 50 pF, 20 40 50 ns
t
f
Differential output fall time
See Figure 3
t
PZH
Propagation delay time, high-impedance-to-high-level output
RE at 0 V,
100 ns
See Figure 6
t
PHZ
Propagation delay time, high-level output-to-high-impedance
t
PZL
Propagation delay time, high-impedance-to-high-level output
RE at 0 V,
100 ns
See Figure 7
t
PLZ
Propagation delay time, high-level output-to-high-impedance
t
d(standby)
Time from an active differential output to standby 2 µs
RE at V
CC
, See Figure 8
t
d(wake)
Wake-up time from standby to an active differential output 8 µs
t
sk(p )
Pulse skew | t
PLH
– t
PHL
| 6 ns
(1) All typical values are at V
CC
= 5 V and 25°C
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