Datasheet

SN65HVD21A
SLLSE36 DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN65HVD21A allows up to 256 connected nodes at moderate data rates (up to 6 Mbps). The driver output
slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise
emissions.
The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of
the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence
of any active transmitters on the bus. This feature prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling.
The SN65HVD21A is characterized for operation over the temperature range of –40°C to 85°C.
PRODUCT SELECTION GUIDE
PART NUMBERS CABLE LENGTH AND SIGNALING RATE
(1)
NODES MARKING
SN65HVD21A Up to 150 m at 5 Mbps (with slew rate limit) Up to 256 D: VP21A
(1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.
AVAILABLE OPTIONS
PLASTIC SMALL-OUTLINE
(1)
DPACKAGE
(JEDEC MS-012)
SN65HVD21AD
(1) Add R suffix for taped and reeled carriers.
Table 1. DRIVER FUNCTION TABLE
INPUT ENABLE OUTPUTS
D
DE A B
H H H L
L H L H
X L Z Z
X OPEN Z Z
OPEN H H L
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
Table 2. RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT ENABLE OUTPUT
V
ID
= (V
A
– V
B
) RE R
0.2 V VID L H
–0.2 V < VID < 0.2 V L H (see Note
(1)
)
VID –0.2 V L L
X H Z
X OPEN Z
Open circuit L H
Short Circuit L H
Idle (terminated) bus L H
H = high level, L= low level, Z = high impedance (off)
(1) If the differential input V
ID
remains within the transition range for
more than 250 µs, the integrated failsafe circuitry detects a bus fault,
and set the receiver output to a high state. See Figure 15.
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