Datasheet

V
OC
27 1%W ±
27 1%W ±
Input
A
B
V
A
V
B
V
OC(PP)
DV
OC(SS)
V
OC
C =50pF
L
±20%
D
A
B
DE
V
CC
C IncludesFixtureand
L
InstrumentationCapacitance
S0302-01
60 1%W ±
V
OD
0Vor3V
_
+
–20V<V(test)<25V
DE
V
CC
A
B
D
375 1%W ±
375 1%W ±
S0301-01
SN65HVD1794, SN65HVD1795
SN65HVD1796
SLLS935A –AUGUST 2008–REVISED AUGUST 2012 www.ti.com
THERMAL INFORMATION
PARAMETER TEST CONDITIONS VALUE UNIT
JEDEC high-K model 138
SOIC-8
JEDIC low-K model 242
R
θJA
Junction-to-ambient thermal resistance (no airflow) °C/W
JEDEC high-K model 59
DIP-8
JEDIC low-K model 128
SOIC-8 62
R
θJB
Junction-to-board thermal resistance °C/W
DIP-8 39
SOIC-8 61
R
θJC
Junction-to-case thermal resistance °C/W
DIP-8 61
V
CC
= 5.5 V, T
J
= 150°C, R
L
= 300 Ω,
94 C
L
= 50 pF (driver), C
L
= 15 pF (receiver) 290
5-V supply, unterminated
(1)
94 V
CC
= 5.5 V, T
J
= 150°C, R
L
= 100 Ω,
C
L
= 50 pF (driver), C
L
= 15 pF (receiver)
95 320
5-V supply, RS-422 load
(1)
P
D
Power dissipation mW
96
94 V
CC
= 5.5 V, T
J
= 150°C, R
L
= 54 Ω, 400
C
L
= 50 pF (driver), C
L
= 15 pF (receiver)
95
5-V supply, RS-485 load
(1)
96
T
SD
Thermal-shutdown junction temperature 170 °C
(1) Driver enabled, 50% duty cycle square-wave signal at signaling rate: 115 kbps for HVD1794, 1 Mbps for HVD1795, 10 Mbps for
HVD1796
PARAMETER MEASUREMENT INFORMATION
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
Figure 2. Measurement of Driver Differential Output Voltage With Common-Mode Load
Figure 3. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
6 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Links: SN65HVD1794, SN65HVD1795 SN65HVD1796