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PARAMETER MEASUREMENT INFORMATION
60 Ω ±1%
V
OD
0 or 3 V
_
+
−7 V < V
(test)
< 12 V
DE
V
CC
A
B
D
375 Ω ±1%
375 Ω ±1%
I
OA
V
OD
54 Ω ±1%
0 or 3 V
V
OA
V
OB
I
OB
DE
V
CC
I
I
V
I
A
B
V
OC
27 Ω ± 1%
Input
A
B
V
A
V
B
V
OC(PP)
∆V
OC(SS)
V
OC
27 Ω ± 1%
C
L
= 50 pF ±20%
D
A
B
DE
V
CC
Input: PRR = 500 kHz, 50% Duty Cycle, t
r
< 6 ns, t
f
< 6 ns, Z
O
= 50 Ω
C
L
Includes Fixture and
Instrumentation Capacitance
V
OD
R
L
= 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
< 6 ns, t
f
< 6 ns, Z
o
= 50 Ω
t
PLH
t
PHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ −2 V
90%
10%
0 V
V
I
V
OD
t
r
t
f
C
L
= 50 pF ±20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
CC
V
I
Input
Generator
90%
0 V
10%
R
L
= 110 Ω
± 1%
Input
Generator
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
< 6 ns, t
f
< 6 ns, Z
o
= 50 Ω
3 V
S1
0.5 V
3 V
0 V
V
OH
≈ 0 V
t
PHZ
t
PZH
1.5 V 1.5 V
V
I
V
O
C
L
= 50 pF ±20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
O
V
I
2.3 V
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
Figure 2. Driver V
OD
Test Circuit and Voltage and Figure 3. Driver V
OD
With Common-Mode Loading Test
Current Definitions Circuit
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
Figure 6. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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