Datasheet
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
THERMAL CHARACTERISTICS
(1)
SN65HVD10-EP , , SN65HVD11-EP
SN65HVD12-EP
SGLS278E – DECEMBER 2004 – REVISED SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high level output HVD10 12.5 20 25 ns
t
PHL
Propagation delay time, high-to-low level output HVD10 12.5 20 25 ns
HVD11
t
PLH
Propagation delay time, low-to-high level output 30 55 70 ns
HVD12
V
ID
= – 1.5 V to 1.5 V,
HVD11
t
PHL
Propagation delay time, high-to-low level output C
L
= 15 pF, See Figure 9 30 55 70 ns
HVD12
HVD10 1.5
t
sk(p)
Pulse skew (|t
PHL
- t
PLH
|) HVD11 4 ns
HVD12 4
HVD10 8
t
sk(pp)
(2)
Part-to-part skew HVD11 15 ns
HVD12 15
t
r
Output signal rise time 1 2 6
C
L
= 15 pF, See Figure 9 ns
t
f
Output signal fall time 1 2 6
t
PZH
(1)
Output enable time to high level 16
t
PZL
(1)
Output enable time to low level 16
C
L
= 15 pF, DE at 3 V,
ns
See Figure 10
t
PHZ
Output disable time from high level 21
t
PLZ
Output disable time from low level 16
I and
6
Propagation delay time, standby-to-high-level
Q-temp
t
PZH
(2)
output
M-temp 14
C
L
= 15 pF, DE at 0,
μ s
See Figure 11
I and
6
Propagation delay time, standby-to-low-level
Q-temp
t
PZL
(2)
output
M-temp 14
(1) All typical values are at 25 ° C and with a 3.3 V supply.
(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θ
JA
Junction-to-ambient thermal resistance
(2)
High-K board
(3)
, No airflow D package 121 ° C/W
θ
JB
Junction-to-board thermal resistance High-K board D package 67 ° C/W
θ
JC
Junction-to-case thermal resistance D package 41 ° C/W
HVD10
198 233 mW
(25 Mbps)
R
L
= 60 Ω , C
L
= 50 pF,
DE at V
CC
RE at 0 V, HVD11
P
D
Device power dissipation 141 176 mW
Input to D a 50% duty cycle square (10 Mbps)
wave at indicated signaling rate
HVD12
133 161 mW
(500 kbps)
T
JSD
Thermal shutdown junction temperature 165 ° C
(1) See Application Information section for an explanation of these parameters.
(2) The intent of θ
JA
specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JSD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
8 Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10-EP SN65HVD11-EP SN65HVD12-EP