Datasheet
SN65HVD1050-Q1
SLLS696C –MAY 2006–REVISED DECEMBER 2010
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DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Total loop delay, driver input to receiver output,
t
d(LOOP1)
S at 0 V, See Figure 9 90 230 ns
recessive to dominant
Total loop delay, driver input to receiver output,
t
d(LOOP2)
S at 0 V, See Figure 9 90 230 ns
dominant to recessive
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
CANH 2.9 3.4 4.5
V
I
= 0 V, S at 0 V, R
L
= 60 Ω, See Figure 1
V
O(D)
Bus output voltage (dominant) V
and Figure 2
CANL 0.8 1.5
V
I
= 3 V, S at 0 V, R
L
= 60 Ω, See Figure 1
V
O(R)
Bus output voltage (recessive) 2 2.3 3 V
and Figure 2
V
I
= 0 V, R
L
= 60 Ω, S at 0 V, See Figure 1,
1.5 3 V
Figure 2, and Figure 3
V
OD(D)
Differential output voltage (dominant)
V
I
= 0 V, R
L
= 45 Ω, S at 0 V, See Figure 1,
1.4 3 V
Figure 2, and Figure 3
V
I
= 3 V, S at 0 V, See Figure 1 and Figure 2 –0.012 0.012
V
OD(R)
Differential output voltage (recessive) V
V
I
= 3 V, S at 0 V, No Load –0.5 0.05
Steady state common-mode output
V
OC(ss)
2 2.3 3 V
voltage
S at 0 V, Figure 8
Change in steady-state common-mode
ΔV
OC(ss)
30 mV
output voltage
I
IH
High-level input current, TXD input V
I
at V
CC
–2 2
I
IL
Low-level input current, TXD input V
I
at 0 V –50 –10 mA
I
O(off)
Power-off TXD output current V
CC
at 0 V, TXD at 5 V 1
V
CANH
= –12 V, CANL open, See Figure 11 –105 –72
V
CANH
= 12 V, CANL open, See Figure 11 0.36 1
I
OS(ss)
Short-circuit steady-state output current mA
V
CANL
= –12 V, CANH open, See Figure 11 –1 –0.5
V
CANL
= 12 V, CANH open, See Figure 11 71 105
C
O
Output capacitance See receiver input capacitance
(1) All typical values are at 25°C with a 5-V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high level output S at 0 V, See Figure 4 25 65 120 ns
t
PHL
Propagation delay time, high-to-low level output S at 0 V, See Figure 4 25 45 120 ns
t
r
Differential output signal rise time S at 0 V, See Figure 4 25 ns
t
f
Differential output signal fall time S at 0 V, See Figure 4 50 ns
t
en
Enable time from silent mode to dominant See Figure 7 1 ms
t
(dom)
Dominant time out ↓V
I
, See Figure 10 300 450 700 ms
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