Datasheet

CANH
CANL
TXD
S
V
I
47 nF
+20%
27 W +1%
27 W +1%
V
OC
=
V
O(CANH)
+ V
O(CANL)
2
DV
OC(SS)
V
OC
+
_
DUT
TXD
S
RXD
V
I
C
L
CANH
CANL
NOTE:C
L
=100pF
includesinstrumentation
andfixturecapacitance
within±20%
V
O
50%
50%
50%
V
CC
0V
V
OH
V
OL
TXDInput
RXDOutput
t
loop2
t
loop1
15pF±20%
60
±1%
W
S
CANH
V
I
TXD
(See Note A)
R
L
= 60 W
+1%
C
L
(See Note B)
V
OD
t
dom
V
I
900 mV
V
OD
500 mV
V
CC
0 V
V
OD(D)
0 V
SN65HVD1050
www.ti.com SLLS632B –DECEMBER 2005–REVISED MARCH 2010
NOTE: All V
I
input pulses are from 0 V to V
CC
and supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common Mode Output Voltage Test and Waveforms
A. All V
I
input pulses are from 0 V to V
CC
and supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t
(LOOP)
Test Circuit and Waveform
A. All V
I
input pulses are from 0 V to V
CC
and supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B. C
L
= 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 10. Dominant Time-Out Test Circuit and Waveforms
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s) :SN65HVD1050