Datasheet

+
_
DUT
TXD
STB
RXD
15 pF 20%±
V
O
V
I
0 V C
L
(A)
60 W
±1%
CANH
CANL
0.5 V
CC
0.5 V
CC
t
en
V
CC
0 V
V
OH
V
OL
V
I
(B)
V
O
CANH
CANL
TXD
STB
V
I
V
O(CANH)
V
OC(SS)
R
L
V
O(CANL)
V =
OC
2
V + V
O(CANH) O(CANL)
V
OC
+
_
DUT
TXD
STB
RXD
V
I
(B)
C
L
(A)
CANH
CANL
V
O
0.5V
CC
0.5V
CC
0.5V
CC
V
CC
0V
V
OH
V
OL
TXDInput
RXDOutput
t
loop2
t
loop1
15pF±20%
60
±1%
W
SN65HVD1040-Q1
www.ti.com SLLS753D –FEBRUARY 2007– REVISED AUGUST 2011
A. C
L
= 100 pF and includes instrumentation and fixture capacitance within ±20%.
B. All V
I
input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 7. t
en
Test Circuit and Waveforms
NOTE: All V
I
input pulses are from 0 V to V
CC
and supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. Common-Mode Output Voltage Test and Waveforms
A. C
L
= 100 pF and includes instrumentation and fixture capacitance within ±20%.
B. All V
I
input pulses are from 0 V to V
CC
and supplied by a generator having the following characteristics: t
r
or t
f
≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t
(LOOP)
Test Circuit and Waveforms
Copyright © 2007–2011, Texas Instruments Incorporated 9