Datasheet
50%
50%50%
NOTE: C
L
= 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
CANH
CANL
C
L
TXD
STB
RXD
+
V
O
−
15 pF 20%
DUT
60 W 1%
TXD
Input
RXD Output
t
loop2
t
loop1
V
CC
0 V
V
OH
V
OL
STB
CANH
CANL
V
O
500 mV
900 mV
C
L
(see Note B)
R
L
= 60 W +1%
TXD
(see Note A)
V
I
V
O
t
dom
V
CC
0 V
V
OD(D)
0 V
V
I
1.5 V
CANH
CANL
RXD
V
O
V
I
I
O
C
L
STB
3.5 V
V
I
V
O
400 mV
2.65 V
1.5 V
V
OH
V
OL
(see Note A)
V
CC
(see Note B)
0.7 s
t
BUS
SN65HVD1040
SLLS631D – MARCH 2007 – REVISED DECEMBER 2008 ...............................................................................................................................................
www.ti.com
A. All V
I
input pulses are from 0 V to V
CC
and supplied by a generator with the following characteristics: t
r
or t
f
≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. t
loop
Test Circuit and Voltage Waveforms
A. All V
I
input pulses are from 0 V to V
CC
and supplied by a generator with the following characteristics: t
r
or t
f
≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B. C
L
= 100 pF includes instrumentation and fixture capacitance within ± 20%.
Figure 10. Dominant Time-Out Test Circuit and Waveform
A. For V
I
bit width ≤ 0.7 µ s, V
O
= V
OH
. For V
I
I bit width ≥ 5 µ s, V
O
= V
OL
. V
I
input pulses are supplied from a generator
with the following characteristics; t
r
or t
f
≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B. C
L
= 15 pF includes instrumentation and fixture capacitance within ± 20%.
Figure 11. t
BUS
Test Circuit and Waveform
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