Datasheet
SN65HVD1040A-Q1
SLLS889B –JUNE 2008–REVISED SEPTEMBER 2011
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RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output STB at 0 V , See Figure 6 60 90 130 ns
t
PHL
Propagation delay time, high-to-low-level output STB at 0 V , See Figure 6 45 70 130 ns
t
r
Output signal rise time STB at 0 V , See Figure 6 8 ns
t
f
Output signal fall time STB at 0 V , See Figure 6 8 ns
t
BUS
Dominant time required on bus for wake-up from standby STB at V
CC
, See Figure 12 1.5 5 μs
(1) All typical values are at 25°C with a 5-V supply.
STB PIN CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
I
IH
High-level input current STB at V
CC
–10 0 μA
I
IL
Low-level input current STB at 0 V –10 0 μA
SPLIT PIN CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
O
Output voltage –500 μA < I
O
< 500 μA 0.3 V
CC
0.5 V
CC
0.7 V
CC
V
I
O(stb)
Leakage current, standby mode STB at 2 V, –12 V ≤ V
O
≤ 12 V –5 5 μA
(1) All typical values are at 25°C with a 5-V supply.
THERMAL CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K thermal resistance
(2)
211
θ
JA
Junction-to-air thermal resistance
(1)
°C/W
High-K thermal resistance
(2)
131
θ
JB
Junction-to-board thermal resistance 53 °C/W
θ
JC
Junction-to-case thermal resistance 79 °C/W
V
CC
= 5 V, T
J
= 27°C, R
L
= 60 Ω, STB at 0 V,
Input to TXD at 500 kHz, 50% duty cycle 112
square wave, C
L
at RXD = 15 pF
P
D
Average power dissipation mW
V
CC
= 5.5 V, T
J
= 130°C, R
L
= 45 Ω, STB at 0 V,
Input to TXD at 500 kHz, 50% duty cycle 170
square wave, C
L
at RXD = 15 pF
Thermal shutdown temperature 185 °C
(1) The junction temperature (T
J
) is calculated using the following T
J
= T
A
+ (P
D
× θ
JA
).
(2) Tested in accordance with the Low-K (EIA/JESD51-3) or High-K (EIA/JESD51-7) thermal metric definitions for leaded surface-mount
packages.
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