Datasheet

SN65HVD1040A-Q1
www.ti.com SLLS889B –JUNE 2008– REVISED SEPTEMBER 2011
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high level output STB at 0 V, See Figure 4 25 65 120 ns
t
PHL
Propagation delay time, high-to-low level output STB at 0 V, See Figure 4 25 45 120 ns
t
r
Differential output signal rise time STB at 0 V, See Figure 4 25 ns
t
f
Differential output signal fall time STB at 0 V, See Figure 4 45 ns
t
en
Enable time from standby mode to dominant See Figure 7 10 μs
t
(dom)
Dominant time out
(2)
↓V
I
, See Figure 10 300 450 700 μs
(1) All typical values are at 25°C with a 5-V supply.
(2) The TXD dominant time out (t
(dom)
) disables the driver of the transceiver once the TXD has been dominant longer than t
(dom)
, which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t
(dom)
minimum, limits the minimum
bit rate. The minimum bit rate may be calculated by:
Minimum Bit Rate = 11/ t
(dom)
= 11 bits / 300 μs = 37 kbps
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions, T
A
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Positive-going input threshold voltage,
V
IT+
STB at 0 V, See Table 3 800 900 mV
high-speed mode
Negative-going input threshold voltage,
V
IT–
STB at 0 V, See Table 3 500 650 mV
high-speed mode
V
hys
Hysteresis voltage (V
IT+
– V
IT–
) 100 125 mV
V
IT
Input threshold voltage, standby mode STB at V
CC
500 1150 mV
V
OH
High-level output voltage I
O
= –2 mA, See Figure 6 4 4.6 V
V
OL
Low-level output voltage I
O
= 2 mA, See Figure 6 0.2 0.4 V
CANH = CANL = 5 V,
I
I(off)
Power-off bus input current 3 μA
V
CC
at 0 V, TXD at 0 V
I
O(off)
Power-off RXD leakage current V
CC
at 0 V, RXD at 5 V 20 μA
TXD at 3 V,
C
I
Input capacitance to ground (CANH or CANL) 13 pF
V
I
= 0.4 sin (4E6πt) + 2.5 V
C
ID
Differential input capacitance TXD at 3 V, V
I
= 0.4 sin (4E6πt) 6 pF
R
ID
Differential input resistance TXD at 3 V, STB at 0 V 30 80 kΩ
R
IN
Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 30 40 kΩ
Input resistance matching
R
I(m)
V
(CANH)
= V
(CANL)
–3 0 3 %
[1 – (R
IN (CANH)
/ R
IN (CANL)
)] × 100%
(1) All typical values are at 25°C with a 5-V supply.
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