Datasheet

V
OC
27 Ω ± 1%
Input
A
B
V
A
V
B
V
OC(PP)
∆V
OC(SS)
V
OC
27 Ω ± 1%
C
L
= 50 pF ±20%
D
A
B
DE
V
CC
Input: PRR = 500 kHz, 50% Duty Cycle,t
r
<6ns, t
f
<6ns, Z
O
= 50 Ω
C
L
Includes Fixture and
Instrumentation Capacitance
V
OD
R
L
= 54 Ω
± 1%
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50 Ω
t
PLH
t
PHL
1.5 V 1.5 V
3 V
≈ 2 V
≈ –2 V
90%
10%
0 V
V
I
V
OD
t
r
t
f
C
L
= 50 pF ±20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
CC
V
I
Input
Generator
90%
0 V
10%
0 V
R
L
= 110 Ω
± 1%
Input
Generator
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50 Ω
3 V
S1
0.5 V
3 V
0 V
V
OH
≈ 0 V
t
PHZ
t
PZH(1 & 2)
1.5 V 1.5 V
V
I
V
O
C
L
= 50 pF ±20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
O
V
I
2.3 V
Input
Generator
50 Ω
3 V
V
O
S1
1.5 V 1.5 V
t
PLZ
2.3 V
0.5 V
≈ 3 V
0 V
V
OL
V
I
V
O
Generator: PRR = 100 kHz, 50% Duty Cycle, t
r
<6 ns, t
f
<6 ns, Z
o
= 50 Ω
R
L
= 110 Ω
± 1%
C
L
= 50 pF ±20%
C
L
Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
V
I
t
PZL(1 & 2)
V
CC
V
CC
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com SLLS533E –MAY 2002– REVISED AUGUST 2009
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
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Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07