Datasheet

50 Ω
Generator: PRR = 100 kHz,
50% Duty Cycle,
t
r
<6 ns, t
f
<6 ns, Z
o
= 50 Ω
V
O
RE
V
CC
0 V or 3 V
1.5 V 1.5 V
t
PZH(1)
t
PHZ
1.5 V
V
OH
–0.5 V
3 V
0 V
V
OH
≈ 0 V
V
O
C
L
= 15 pF ±20%
C
L
Includes Fixture and
Instrumentation Capacitance
V
I
DE
D
1 kΩ ± 1%
V
I
A
B
S1
D at 3 V
S1 to B
t
PZL(1)
t
PLZ
1.5 V
V
OL
+0.5 V
V
OL
V
O
D at 0 V
S1 to A
Input
Generator
R
3 V
A
B
V
CC
SN65HVD05, SN65HVD06
SN75HVD05, SN65HVD07
SN75HVD06, SN75HVD07
www.ti.com SLLS533E –MAY 2002– REVISED AUGUST 2009
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Copyright © 2002–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65HVD05 SN65HVD06 SN75HVD05 SN65HVD07 SN75HVD06 SN75HVD07