2−GBPS Differential Repeater Evaluation Module User’s Guide November 2002 High-Performance Linear/Interface Products SLLU040A
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the supply voltage range of 3 V to 3.6 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the supply range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Information About Cautions and Warnings Preface Read This First About This Manual This EVM user’s guide provides information about the 2-GBPS differential repeater evaluation module. How to Use This Manual This document contains the following chapters: - Chapter 1 — Introduction - Chapter2 — Setup and Equipment Required - Chapter 3 — EVM Construction Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . .
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Chapter 1 Introduction The 2-GBPS differential repeater evaluation module (EVM) allows evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. This user’s guide gives a brief overview of the EVM, setup and operation instructions, and typical test results that can be expected. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . .
Overview 1.1 Overview The 2-GBPS differential repeater evaluation module (EVM) is designed for evaluation of the SN65LVDS100, SN65LVDS101, and SN65CML100 differential repeaters/ translators. The SN65LVDS100 and SN65LVDS101 devices both incorporate wide common-mode range receivers, allowing receipt of LVDS, LVPECL, or CML input signals. The SN65LVDS100 provides an LVDS output, the SN65LVDS101 incorporates an LVPECL output driver, and the SN65CML100 delivers a CML output.
Signal Paths 1.2 Signal Paths A partial schematic of the EVM is shown in Figure 1-2 and a full schematic is in chapter 3. Edge-mount SMA connectors (J4, J5, J6, and J7) are provided for data input and output connections. Three power jacks (J1, J2, and J3) are used to provide power to and a ground reference, for the EVM. The use of these power jacks is addressed later. Chapter 3 also provides a parts list for the EVM, as well as an indication of which components are installed when shipped. Figure 1-2.
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Chapter 2 Setup and Equipment Required This chapter examines the setup and use of the evaluation module and the results of operation. Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.
Overview 2.1 Overview LVDS driver output characteristics are specified in the TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential signal, with a 1.25-V offset from ground. These levels are attained when driving a 100-Ω differential line-termination test load (see Figure 2-1). In real applications, there may be a ground potential between a driver and receiver(s). The driver must drive the common-mode load presented by the receiver inputs and the differential load.
Applying an Input Figure 2-2. EVM Power Connections for SN65LVDS100 Evaluation Power Supply 1 + 3.3V - Power Supply 2 + 1.22V J3 DUT GND J2 EVM GND J4 J5 J1 VCC J6 100 Ω J7 50 Ω Pattern Generator Matched Cables SMA to SMA 50 Ω Matched Cables SMA to SMA EVM Oscilloscope Warning Power jacks J1, J2, and J3 are not insulated on the backside of the EVM. Place on a nonconductive surface. 2.2 Applying an Input LVDS inputs should be applied to SMA connectors J4 and J5, while keeping R1 installed.
Applying an Input with 50-Ω pullups to VTT. When using external terminations, the onboard termination resistor R1 should be removed from the EVM. It should be noted that the signal quality at the receiver input may be degraded when external terminations are used, as a significant stub exists from the external termination network to the receiver input. The user needs to verify that the transition time of the input signal, coupled with the stub length, does not lead to reflection problems.
Observing an Output Figure 2-4. External Termination for Single-Ended LVPECL Inputs to EVM A OUT Y 50 Ω Signal Source EVM BOARD B Z NOTES: A. Add jumper Jmp2 and 0-Ω R5 B. Remove R1 2.3 Observing an Output Direct connection to an oscilloscope with 50-Ω internal terminations to ground is accomplished without R2, R3, and R41. The outputs are available at J6 and J7 for direct connection to oscilloscope inputs.
Typical Test Results LVPECL drivers need a 50-Ω termination to VT. A modification of Figure 2-2 and the above instructions are used when evaluating an SN65LVDS101 with a direct connection to a 50-Ω oscilloscope. With power supply 1 in Figure 2-2 set to 3.3 V, power supply 2 should be set to 1.3 V (2 V below VCC) to provide the correct termination voltage. CML drivers need a 50-Ω termination to VTT (VTT is either VCC, 2.5 V, or 1.8 V).
Typical Test Results Figure 2-5.
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Chapter 3 EVM Construction This chapter lists the EVM components and examines the construction of the evaluation module. Topic Page 3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.
Schematic 3.1 Schematic VCC J1 -1 + C1 10 µF + C6 10 µF + C2 68 µF C5 0.001 µF C4 0.1 µF C3 1 µF J2 -1 + C8 1 µF C7 68 µF 109 0.001 µF C9 0.1 µF J3 -1 VCC01 VCC J4 GND J5 GND 1 R1 100 Ω 1 R5 Uninstalled DUT1 1 VCC NC 2 Y A 3 B Z 4 GND Vbb DUT_MSOP8 MNTH4 MNTH3 MNTH2 1 VCC01 C12 .010 µF J6 GND R4 Uninstalled 1 Uninstalled 2 MNTH1 C11 .
Bill of Materials 3.2 Bill of Materials † ITEM QTY MFG MFG PART NO. REF. DES. DESCRIPTION VALUE OR FUNCTION 1 2 Sprague 293D106X0035D2W C1,C6 Capacitor, SMT, TANT 35 V, 10%, 10 µF 2 2 AVX 12063G105ZATRA C3,C8 Capacitor, SMT1206 25 V, 80 -20%, 1.0 µF 3 2 AVX 12065C104JATMA C4,C9 Capacitor, SMT1206 50 V, 5%, 0.1 µF 4 2 Sprague 592D686X0010R2T C2,C7 Capacitor, SMT, TANT 10 V, 20%, 68 µF, Low ESR 5 2 Murata GRM39X7R103K50V C11, C12 Capacitor, SMT0603 50 V,±10%, 0.
Board Stackup 3.3 Board Stackup GENERAL NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL FABRICATION ITEMS MUST MEET OR EXCEED BEST INDUSTRY PRACTICE. IPC-A 600C ( Commercial Std.) 2.LAMINATE MATERIAL: NELCO N4000-13 (DO NOT USE - 13SI) 3. COOPER WEIGHT:1 OZ. START INTERNAL AND 1/2 OZ. START EXTERNAL 4. FINISHED BOARD THICKNESS: .062 ±10% 5. MAXIMUM WARP AND TWIST TO BE .005 INCH PER INCH 6 MINIMUM COPPER WALL THICKNESS OF PLATED-THRU HOLES TO BE .001 INCH 7 MINIMUM ANNULAR RING OF PLATED-THRU HOLES TO BE .
Board Layer Patterns 3.
Board Layer Patterns Layer 3 - VCC Split Plane (INT2) Layer 4 - GND Plane (Bottom Side) 3-6
