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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
3.3 V or 5 V
SN65CML100
3.3 V
50 Ω
50 Ω
A
B
50 Ω
50 Ω
V
TT
V
TT
= V
CC
-2 V
ECL
3.3 V
SN65CML100
3.3 V
50 Ω
50 Ω
A
B
CML
V
TT
3.3 V
SN65CML100
3.3 V
50 Ω
A
B
50 Ω
ECL
V
BB
V
TT
V
TT
= V
CC
-2 V
3.3 V or 5 V
SN65CML100
3.3 V
50 Ω
50 Ω
A
B
100 Ω
LVDS
SN65CML100
SLLS547 – NOVEMBER 2002
For single-ended input conditions, the unused differential input is connected to V
BB
as a switching reference
voltage. When V
BB
is used, decouple V
BB
via a 0.01- µ F capacitor and limit the current sourcing or sinking to 0.4
mA. When not used, V
BB
should be left open.
Figure 24. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Figure 25. Current-Mode Logic (CML)
Figure 26. Single-Ended (LVPECL)
Figure 27. Low-Voltage Differential Signaling (LVDS)
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