Datasheet

SN65175, SN75175
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS145C − OCTOBER 1990 − REVISED NOVEMBER 2006
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage and operating free-air temperature
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT+
Positive-going input threshold voltage V
O
= 2.7 V, I
O
= −0.4 mA 0.2 V
V
IT−
Negative-going input threshold voltage V
O
= 0.5 V, I
O
= 16 mA −0.2
‡
V
V
hys
Hysteresis voltage (V
IT+
− V
IT−
) See Figure 4 50 mV
V
IK
Enable-input clamp voltage I
I
= −18 mA −1.5 V
V
OH
High-level output voltage V
ID
= 200 mV, I
OH
= −400 µA, See Figure 1 2.7 V
V
Low level output voltage
V 200 mV
See Figure 1
I
OL
= 8 mA 0.45
V
V
OL
Low-level output voltage V
ID
= −200 mV, See Figure 1
I
OL
= 16 mA 0.5
V
I
OZ
High-impedance-state output current V
O
= 0.4 V to 2.4 V ± 20 µA
I
Line input current
Other input at 0 V
See Note 3
V
I
= 12 V 1
mA
I
I
Line input current Other input at 0 V, See Note 3
V
I
= − 7 V −0.8
mA
I
IH
High-level enable-input current V
IH
= 2.7 V 20 µA
I
IL
Low-level enable-input current V
IL
= 0.4 V −100 µA
r
i
Input resistance 12 kΩ
I
OS
Short-circuit output current
§
−15 −85 mA
I
CC
Supply current Outputs disabled 70 mA
†
All typical values are at V
CC
= 5 V, T
A
= 25°C.
‡
The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage
levels only.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 3: Refer to ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485 for exact conditions.
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level output
See Figure 2
22 35 ns
t
PHL
Propagation delay time, high- to low-level output
See Figure 2
25 35 ns
t
PZH
Output enable time to high level
See Figure 3
13 30 ns
t
PZL
Output enable time to low level
See Figure 3
19 30 ns
t
PHZ
Output disable time from high level
See Figure 3
26 35 ns
t
PLZ
Output disable time from low level
See Figure 3
25 35 ns