Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 24

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

SCBS477 − DECEMBER 1992 − REVISED JANUARY 1994



3−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• State-of-the-Art BiCMOS Design

Significantly Reduces I

CCZ

• High-Impedance State During Power Up and

Power Down

• ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model (C = 200 pF,

R = 0)

• Designed to Facilitate Incident-Wave

Switching for Line Impedances of 25 Ω or

Greater

• Distributed V

and GND Pins Minimize

Noise Generated by the Simultaneous

Switching of Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic 300-mil DIPs (NT)

description

The SN64BCT25244 is a 25-Ω octal buffer and line driver designed specifically to improve both the performance

and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.

When the output-enable (1OE

and 2OE) inputs are low, the device transmits data from the A inputs to the

Y outputs. When 1OE

and 2OE are high, the outputs are in the high-impedance state.

This buffer/driver is capable of sinking 188-mA I

, which facilitates switching 25-Ω transmission lines on the

incident wave. The distributed V

and GND pins minimize switching noise for more reliable system operation.

The outputs are in a high-impedance state during power up and power down while the supply voltage value is

less than approximately 3 V.

The SN64BCT25244 is characterized for operation from −40°C to 85°C and 0°C to 70°C.

FUNCTION TABLE

(each buffer/driver)

INPUTS

OUTPUT

OE A

OUTPUT

L H H

L LL

H X Z

1Y1

GND

1Y2

1Y3

GND

1Y4

2Y1

GND

2Y2

2Y3

GND

2Y4

1OE

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

2OE

DW OR NT PACKAGE

(TOP VIEW)

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Summary of content (8 pages)

PAGE 1
Ω SCBS477 − DECEMBER 1992 − REVISED JANUARY 1994 • • • • • • DW OR NT PACKAGE (TOP VIEW) State-of-the-Art BiCMOS Design Significantly Reduces ICCZ High-Impedance State During Power Up and Power Down ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 Ω or Greater Distributed VCC and GND Pins Minimize Noise Generated
PAGE 2
Ω SCBS477 − DECEMBER 1992 − REVISED JANUARY 1994 logic symbol† 1OE 1A1 1A2 1A3 1A4 24 logic diagram (positive logic) 1OE EN 23 1 22 1 3 20 4 19 6 1A1 1Y1 13 1Y3 1A2 EN 2A1 2A2 2A3 2A4 17 1 7 9 15 10 14 12 1 22 3 20 4 1Y3 19 6 1Y4 1Y1 1Y2 1Y4 1A4 18 23 1Y2 1A3 2OE 24 2Y1 2Y2 2Y3 2OE 13 2Y4 2A1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
Ω SCBS477 − DECEMBER 1992 − REVISED JANUARY 1994 recommended operating conditions (see Note 2) VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL MIN NOM MAX 4.5 5 5.5 High-level input voltage 2 UNIT V V 0.8 V Input clamp current −18 mA High-level output current −80 mA 188 mA 85 °C Low-level output current TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low.
PAGE 4
Ω SCBS477 − DECEMBER 1992 − REVISED JANUARY 1994 3−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 •
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PACKAGE OPTION ADDENDUM www.ti.
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