Datasheet

THERMAL ANALYSIS
P
Dmax
+
T
max
–T
A
q
JA
where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
max
is the absolute maximum junction temperature (°C).
T
A
is the ambient temperature (°C).
θ
JA
= θ
JC
+ θ
CA
θ
JC
is the thermal coefficient from the silicon junctions to the
case (°C/W).
θ
CA
is the thermal coefficient from the case to ambient air
(°C/W).
1.5
1
0
−40 −20 0 20
− Maximum Power Dissipation − W
40 60 80
T
A
− Ambient Temperature − °C
P
D
θ
JA
= 170°C/W for 8-Pin SOIC (D)
θ
JA
= 324.1°C/W for 5-Pin SOT−23 (DBV)
T
J
= 150°C, No Airflow
0.5
8-Pin D Package
1.25
0.25
0.75
5-Pin DBV Package
SN10501
SN10502
SN10503
www.ti.com .................................................................................................................................................. SLOS408B – MARCH 2003 – REVISED JANUARY 2009
with a 2-pF parasitic load. Higher parasitic
capacitive loads without an R
(ISO)
are allowed as
The SN1050x family of devices does not incorporate
the signal gain increases (increasing the
automatic thermal shutoff protection, so the designer
unloaded phase margin). If a long trace is
must take care to ensure that the design does not
required, and the 6-dB signal loss intrinsic to a
violate the absolute-maximum junction temperature of
doubly-terminated transmission line is
the device. Failure may result if the
acceptable, implement a matched-impedance
absolute-maximum junction temperature of 150 ° C is
transmission line using microstrip or stripline
exceeded.
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
The thermal characteristics of the device are dictated
50- Ω environment is normally not necessary
by the package and the PC board. Maximum power
onboard, and in fact a higher-impedance
dissipation for a given package can be calculated
environment improves distortion as shown in the
using the following formula.
distortion-versus-load plots. With a characteristic
board-trace impedance definition based on board
material and trace dimensions, a matching series
resistor in the trace from the output of the
SN1050x is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB
attenuation of a doubly terminated transmission
line is unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case and
add an R
(ISO)
resistor in series with the output to
isolate any capacitance to the amplifier. This
setting does not preserve the signal integrity of a
doubly-terminated line. If the input impedance of
the destination device is low, the signal is
attenuated due to the voltage divider formed by
the series output into the terminating impedance.
5. Socketing a high speed part like the SN1050x
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create a troublesome parasitic
network which can make it almost impossible to
achieve a smooth, stable frequency response.
Best results are obtained by soldering the
Figure 46. Maximum Power Dissipation
SN1050x onto the board.
vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
maximum power dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
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