Datasheet

Overview

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1 Overview

The SMV512K32-SP 16-Mbit asynchronous SRAM is a QML Class-V Radiation-Hardened memory

co-developed with Silicon Space Technology corporation. The HARDSIL™ radiation hardening technology

is an expansion optimization of the radiation performance window by tweaking the processing technology

of the circuit design with the layout of the device. The HARDSIL™ technology provides superior radiation

performance with no SWAP (size, weight and power) tradeoffs.

This ultra high performance asynchronous SRAM is functionally com patible with commercial SRAMs and

is organized as 512K Words by 32 Bits and has 20ns Read, 13.8ns Write maximum access times. Since it

is an Asynchronous Memory, it never needs a clock to refresh the memory and only Reads, Writes,

ChipSelect Address, and Data need to be exercised at any given time.

The memory boasts the industries lowest Standby Current (I

) of 200μA which enables the lowest power

consumption for Space-grade SRAMs enabling significant system-level power savings.

Figure 1 shows the SMV512K32-SP block diagram of key elements.

Figure 1. SMV512K32-SP Block Diagram

The device is pin selectable between Master and Slave modes, and Master-mode provides users with

built-in a user defined autonomous Error-Detection-And-Control (or EDAC) for detecting a single bit error

from a radiation strike in the device. The built-in “Scrub” engine is included for autonomous cleansing of

Single-Event-Errors and avoids multiple errors and a permanent uncorrectable “Multiple-Bit-Error”. The

combination of the EDAC and Scrub delivers Soft-Error-Rates (SER) < 5e

-17

upsets per bit-day. This is the

lowest architecture and power overhead for autonomous Soft-Error mitigation.

The SRAM is Latch up immunity > Linear Energy Transfer (LET) of 110 MeV-cm2/mg which ensures

reliable memory data integrity under harshest conditions (T=125°C).

It has a three-state bidirectional data bus and has CMOS compatible Input and Output levels. The Core is

powered with a 1.8V ±0.15V CORE and the I/O’s with a 3.3V ±0.3V supply.

The SMV512K32-SP device is offered in a 76-pin Ceramic QFP package, which is shown in Figure 2

below.

SMV512K32-CVAL SRAM Breakout Evaluation Board SLVU571– January 2012

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