Datasheet

D
OUT
CS
V
IH
t
DIS
90%
10%
90%
10%
D
OUT
90%
10%
SCLK
CS
t
CSS
1 2
t
CSH
V
IL
0.7 x V
IO
0.3 x V
IO
D
OUT
SCLK
t
DH
t
DA
D
OUT
t
f
t
r
0.9 x V
IO
0.1 x V
IO
1.6V
TO OUTPUT
PIN
CL
25 pF
I
OH
I
OL
2 mA
2 mA
SM73201
www.ti.com SNOSB89B –JUNE 2011–REVISED JUNE 2013
Figure 3. Timing Test Circuit
Figure 4. D
OUT
Rise and Fall Times
Figure 5. D
OUT
Hold and Access Times
Figure 6. Valid CS Assertion Times
Figure 7. Voltage Waveform for t
DIS
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