Datasheet
4 5 13 14 15 16 17
18
t
ACQ
(Power-Down)
t
CONV
(Power-Up)
D15
D5 D4 D3 D2
1
DOUT
SCLK
CS
2 3
0
1
D1
D0
2
t
DIS
t
CH
0
D14
t
CL
t
EN
t
CS
SM73201
SNOSB89B –JUNE 2011–REVISED JUNE 2013
www.ti.com
SM73201 Converter Electrical Characteristics
(1)
(continued)
The following specifications apply for V
A
= 4.5V to 5.5V, V
IO
= 2.7V to 5.5V, and V
REF
= 2.5V to 5.5V for f
SCLK
= 1 MHz to 4
MHz or V
REF
= 4.5V to 5.5V for f
SCLK
= 1 MHz to 5 MHz; f
IN
= 20 kHz, and C
L
= 25 pF, unless otherwise noted. Maximum and
minimum values apply for T
A
= T
MIN
to T
MAX
; the typical values apply for T
A
= 25°C.
Parameter Test Conditions Min Typ Max Units
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Maximum Clock Frequency 1 5 MHz
f
S
Maximum Sample Rate See
(4)
50 250 kSPS
t
ACQ
Acquisition/Track Time 600 ns
SCLK
t
CONV
Conversion/Hold Time 17
cycles
t
AD
Aperture Delay See the Specification Definitions 6 ns
(4) While the maximum sample rate is f
SCLK
/ 20, the actual sample rate may be lower than this by having the CS rate slower than f
SCLK
/
20.
SM73201 Timing Specifications
(1)
The following specifications apply for V
A
= 4.5V to 5.5V, V
IO
= 2.7V to 5.5V, V
REF
= 2.5V to 5.5V, f
SCLK
= 1Mz to 5MHz, and C
L
= 25 pF, unless otherwise noted. Maximum and minimum values apply for T
A
= T
MIN
to T
MAX
; the typical values apply for T
A
=
25°C.
Parameter Min Typ Max Units
t
CSS
CS Setup Time prior to an SCLK rising edge 8 3 ns
t
CSH
CS Hold Time after an SCLK rising edge 8 3
t
DH
D
OUT
Hold Time after an SCLK falling edge 6 11 ns
t
DA
D
OUT
Access Time after an SCLK falling edge 18 41 ns
t
DIS
D
OUT
Disable Time after the rising edge of CS
(2)
20 30 ns
t
CS
Minimum CS Pulse Width 20 ns
t
EN
D
OUT
Enable Time after the 2nd falling edge of SCLK 20 70 ns
t
CH
SCLK High Time 20 ns
t
CL
SCLK Low Time 20 ns
t
r
D
OUT
Rise Time 7 ns
t
f
D
OUT
Fall Time 7 ns
(1) Typical values are at T
J
= 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing
Quality Level).
(2) t
DIS
is the time for D
OUT
to change 10% while being loaded by the Timing Test Circuit.
Timing Diagrams
Figure 2. SM73201 Single Conversion Timing Diagram
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