Datasheet

100:
+
SM73201
V
REF
+IN
- IN
GND
V
A
SCLK
D
OUT
CSB
0.1 PF
10 PF
0.1 PF
+
10 PF
+5V
Controller
LM4020-2.5
V
IO
SM73201
SNOSB89B –JUNE 2011–REVISED JUNE 2013 www.ti.com
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane.
Furthermore, the GND pins on the SM73201 and all the components in the reference circuitry and input signal
chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting
these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other
high power digital device.
APPLICATION CIRCUITS
The following figures are examples of the SM73201 in typical application circuits. These circuits are basic and
will generally require modification for specific circumstances.
Data Acquisition
Figure 36 shows a typical connection diagram for the SM73201 operating at V
A
of +5V. V
REF
is connected to a
2.5V shunt reference, the LM4020-2.5, to define the analog input range of the SM73201 independent of supply
variation on the +5V supply line. The V
REF
pin should be de-coupled to the ground plane by a 0.1 µF ceramic
capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close as
possible to the V
REF
pin while the placement of the tantalum capacitor is less critical. It is also recommended that
the V
A
and V
IO
pins of the SM73201 be de-coupled to ground by a 0.1 µF ceramic capacitor in parallel with a 10
µF tantalum capacitor.
Figure 36. Low cost, low power Data Acquisition System
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