Datasheet

4 5 13 14 15 16 17
18
t
ACQ
(Power-Down)
t
CONV
(Power-Up)
D15
D5 D4 D3 D2
1
DOUT
SCLK
CS
2 3
0
1
D1
D0
2
t
DIS
t
CH
0
D14
t
CL
t
EN
t
CS
SM73201
www.ti.com SNOSB89B –JUNE 2011–REVISED JUNE 2013
Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the 3
rd
falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
the Timing Specification table.
SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is CMOS
compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The SM73201 offers specified performance with the clock rates
indicated in the electrical table.
The SM73201 enters acquisition mode on the 18
th
falling edge of SCLK during a conversion frame. Assuming
that the LSB is clocked into a controller on the 18
th
rising edge of SCLK, there is a minimum acquisition time
period that must be met before a new conversion frame can begin. Other than the 18
th
rising edge of SCLK that
was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition
mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the controller.
Data Output
The data output format of the SM73201 is two’s complement as shown in Figure 28. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. D
OUT
is in a high impedance state for the 1
st
falling edge of SCLK while the 2
nd
SCLK falling edge clocks out a leading zero. The 3
rd
to 18
th
SCLK falling
edges clock out the conversion result, MSB first.
While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for D
OUT
is acceptable. See
Figure 5 for D
OUT
hold (t
DH
) and access (t
DA
) times.
D
OUT
is enabled on the second falling edge of SCLK after the assertion of CS and is disabled on the rising edge
of CS. If CS is raised prior to the 18
th
falling edge of SCLK, the current conversion is aborted and D
OUT
will go
into its high impedance state. A new conversion will begin when CS is driven LOW.
Figure 35. SM73201 Single Conversion Timing Diagram
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