Datasheet

+
R
SAMPLE+
C
SAMPLE+
SW+
-
R
SAMPLE-
C
SAMPLE-
SW-
C
EXT
R
EXT+
R
EXT-
V
IN
+
-
SM73201
SNOSB89B –JUNE 2011–REVISED JUNE 2013 www.ti.com
Input Settling
When the SM73201 enters acquisition (t
ACQ
) mode at the end of the conversion window, the internal sampling
capacitor (C
SAMPLE
) is connected to the ADC input via an internal switch and a series resistor (R
SAMPLE
), as
shown in Figure 34. Typical values for C
SAMPLE
and R
SAMPLE
are 20 pF and 200 ohms respectively. If there is not
a large external capacitor (C
EXT
) at the analog input of the ADC, a voltage spike will be observed at the input
pins. This is a result of C
SAMPLE
and C
EXT
being at different voltage potentials. The magnitude and direction of the
voltage spike depend on the difference between the voltage of C
SAMPLE
and C
EXT
. If the voltage at C
SAMPLE
is
greater than the voltage at C
EXT
, a positive voltage spike will occur. If the opposite is true, a negative voltage
spike will occur. It is not critical for the performance of the SM73201 to filter out the voltage spike. Rather, ensure
that the transient of the spike settles out within t
ACQ
; for recommended solutions, see ANALOG INPUT
CONSIDERATIONS in the Application Information.
Figure 34. ADC Input Capacitors
SERIAL DIGITAL INTERFACE
The SM73201 communicates via a synchronous 3-wire serial interface as shown in Figure 2 or re-shown in
Figure 35 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of the serial data. D
OUT
is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The SM73201's D
OUT
pin
is in a high impedance state when CS is high and for the first clock period after CS is asserted; D
OUT
is active for
the remainder of time when CS is asserted.
The SM73201 samples the differential input upon the assertion of CS. Assertion is defined as bringing the CS pin
to a logic low state. For the first 17 periods of the SCLK following the assertion of CS, the SM73201 is converting
the analog input voltage. On the 18
th
falling edge of SCLK, the SM73201 enters acquisition (t
ACQ
) mode. For the
next three periods of SCLK, the SM73201 is operating in acquisition mode where the ADC input is tracking the
analog input signal applied across +IN and -IN. During acquisition mode, the SM73201 is consuming a minimal
amount of power.
The SM73201 can enter conversion mode (t
CONV
) under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the SM73201 enters conversion mode on the first falling edge
of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the
SM73201 automatically enters conversion mode and the falling edge of CS is seen as the first falling edge of
SCLK. In the third condition, CS and SCLK go low simultaneously and the SM73201 enters conversion mode.
While there is no timing restriction with respect to the falling edges of CS and SCLK, there are minimum setup
and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. See Figure 6 in
the Timing Diagram section for more information.
CS Input
The CS (chip select bar) input is active low and is CMOS compatible. The SM73201 enters conversion mode
when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the SM73201 is always in
acquisition mode and thus consuming the minimum amount of power. Since CS must be asserted to begin a
conversion, the sample rate of the SM73201 is equal to the assertion rate of CS.
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