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Vref

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Controller

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& I/O

16Bit/250KSPS

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SM73201

www.ti.com

SNOSB89B –JUNE 2011–REVISED JUNE 2013

SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

Check for Samples: SM73201

FEATURES

DESCRIPTION

The SM73201 is a 16-bit successive-approximation

234

• Renewable Energy Grade

• Specified Performance from 50 to 250 kSPS

a maximum sampling rate of 250 kSPS. The

• Separate Digital Input/Output Supply

converter features a differential analog input with an

excellent common-mode signal rejection ratio of 85

• True Differential Input

dB, making the SM73201 suitable for noisy

• External Voltage Reference Range of +0.5V to

environments.

The SM73201 operates with a single analog supply

• Wide Input Common-Mode Voltage Range of

) and a separate digital input/output (V

) supply.

0V to V

can range from +4.5V to +5.5V and V

can range

• SPI™/ QSPI™/MICROWIRE Compatible Serial

from +2.7V to +5.5V. This allows a system designer

Interface

to maximize performance and minimize power

consumption by operating the analog portion of the

• Operating Temperature Range of −40°C to

ADC at a V

of +5V while interfacing with a +3.3V

+85°C

controller. The serial data output is binary 2's

• Small VSSOP-10 Package

complement and is SPI compatible.

The performance of the SM73201 is specified over

APPLICATIONS

temperature at clock rates of 1 MHz to 5 MHz and

• PV DC Arc Detect System

reference voltages of +2.5V to +5.5V. The SM73201

• I/O Modules

is available in a small 10-lead VSSOP package. The

high accuracy, differential input, low power

• Solar Data Acquisition

consumption, and small size make the SM73201

• Instrumentation and Control Systems

ideal for direct connection to bridge sensors and

transducers in battery operated systems or remote

KEY SPECIFICATIONS

data acquisition applications.

• Conversion Rate: 50 kSPS to 250 kSPS

• SNR: 93.2 dBc

• SFDR: 108 dBc

• THD: −104 dBc

• Power Consumption

– 200 kSPS, 5V: 5.3 mW

– 250 kSPS, 5V: 5.8 mW

– Power-Down, 5V: 10 μW

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2QSPI is a trademark of Motorola Incorporated.

3SPI is a trademark of Motorola, Incorporated.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC Check for Samples: SM73201 FEATURES DESCRIPTION • • • • • The SM73201 is a 16-bit successive-approximation register (SAR) Analog-to-Digital converter (ADC) with a maximum sampling rate of 250 kSPS. The converter features a differential analog input with an excellent common-mode signal rejection ratio of 85 dB, making the SM73201 suitable for noisy environments.
PAGE 2
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Block Diagram SAR CONTROL VREF SERIAL INTERFACE +IN S/H CDAC -IN COMPARATOR Connection Diagram VREF 1 10 VA +IN 2 9 VIO SM73201 - IN 3 8 SCLK GND 4 7 DOUT GND 5 6 CS Figure 1. 10-Lead VSSOP See Package Number DGS0010A Pin Descriptions Pin No. 2 Name Description 1 VREF Voltage Reference +0.
PAGE 3
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to 6.5V Digital I/O Supply Voltage VIO Voltage on Any Analog Input Pin to GND −0.3V to (VA + 0.3V) Voltage on Any Digital Input Pin to GND −0.
PAGE 4
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Package Thermal Resistance θJA Package 10-lead VSSOP Soldering process must comply with Reflow Temperature Profile specifications. Refer to SNOA549 Reflow temperature profiles are different for lead-free packages. SM73201 Converter Electrical Characteristics (1) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.
PAGE 5
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 SM73201 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
PAGE 6
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com SM73201 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4 MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
PAGE 7
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 IOL 2 mA TO OUTPUT PIN 1.6V CL 25 pF IOH 2 mA Figure 3. Timing Test Circuit 0.9 x VIO DOUT 0.1 x VIO tr tf Figure 4. DOUT Rise and Fall Times SCLK VIL tDA 0.7 x VIO DOUT 0.3 x VIO tDH Figure 5. DOUT Hold and Access Times SCLK 1 2 tCSH tCSS CS Figure 6. Valid CS Assertion Times CS VIH 90% 90% DOUT 10% tDIS 90% DOUT 10% 10% Figure 7.
PAGE 8
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Specification Definitions APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V.
PAGE 9
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
PAGE 10
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 10 SINAD vs. VA THD vs. VA Figure 8. Figure 9. SINAD vs. VREF THD vs. VREF Figure 10. Figure 11. SINAD vs. SCLK FREQUENCY THD vs. SCLK FREQUENCY Figure 12. Figure 13.
PAGE 11
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. SINAD vs. INPUT FREQUENCY THD vs. INPUT FREQUENCY Figure 14. Figure 15. SINAD vs. TEMPERATURE THD vs. TEMPERATURE Figure 16. Figure 17. VA CURRENT vs. VA VA CURRENT vs. SCLK FREQUENCY Figure 18. Figure 19.
PAGE 12
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. 12 VA CURRENT vs. TEMPERATURE VREF CURRENT vs. VREF Figure 20. Figure 21. VREF CURRENT vs. SCLK FREQUENCY VREF CURRENT vs. TEMPERATURE Figure 22. Figure 23. VIO CURRENT vs. VIO VIO CURRENT vs. SCLK FREQUENCY Figure 24. Figure 25.
PAGE 13
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 Typical Performance Characteristics (continued) VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated. VIO CURRENT vs. TEMPERATURE SPECTRAL RESPONSE - 250 kSPS Figure 26. Figure 27.
PAGE 14
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com FUNCTIONAL DESCRIPTION The SM73201 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses a successive approximation register (SAR) architecture based upon capacitive redistribution containing an inherent sample-and-hold function.
PAGE 15
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 Differential Input Operation The transfer curve of the SM73201 for a fully differential input signal is shown in Figure 28. A positive full scale output code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained when (+IN) − (−IN) is greater than or equal to (VREF − 1 LSB). A negative full scale code (1000 0000 0000 0000b or 8000h or -32,768d) will be obtained when [(+IN) − (−IN)] is less than or equal to (−VREF + 1 LSB).
PAGE 16
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com VCM + VREF VCM VCM - VREF RS VREF SRC + SM73201 CS - VCM Figure 30. Single-Ended Input Since the design of the SM73201 is optimized for a differential input, the performance degrades slightly when driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and dynamic characteristics such as SINAD typically degrade by 2 dB.
PAGE 17
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 6 COMMON-MODE VOLTAGE (V) Single-Ended Input 5 VA = 5.0V 3.75 2.5 1.25 0 -1 0.0 1.25 0.75 1.75 2.5 VREF (V) Figure 32. VCM range for single-ended operation Table 1. Allowable VCM Range Input Signal Differential Single-Ended Minimum VCM Maximum VCM VREF / 2 VA − VREF / 2 VREF VA − VREF CMRR By using this differential input, small signals common to both inputs are rejected.
PAGE 18
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Input Settling When the SM73201 enters acquisition (tACQ) mode at the end of the conversion window, the internal sampling capacitor (CSAMPLE) is connected to the ADC input via an internal switch and a series resistor (RSAMPLE), as shown in Figure 34. Typical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms respectively.
PAGE 19
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature, and the characteristics of the individual device.
PAGE 20
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Applications Information OPERATING CONDITIONS We recommend that the following conditions be observed for operation of the SM73201: −40°C ≤ TA ≤ +85°C +4.5V ≤ VA ≤ +5.5V +2.7V ≤ VIO ≤ +5.5V +0.5V ≤ VREF ≤ +5.
PAGE 21
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 Burst Mode Operation Normal operation of the SM73201 requires the SCLK frequency to be 20 times the sample rate and the CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications requiring sample rates below 250 kSPS, the SM73201 should be run with an SCLK frequency of 5 MHz and a CS rate as slow as the system requires. When this is accomplished, the SM73201 is operating in burst mode.
PAGE 22
SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated.
PAGE 23
SM73201 www.ti.com SNOSB89B – JUNE 2011 – REVISED JUNE 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SM73201IMM/NOPB VSSOP DGS 10 SM73201IMME/NOPB VSSOP DGS SM73201IMMX/NOPB VSSOP DGS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SM73201IMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 SM73201IMME/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 SM73201IMMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
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