Datasheet

UVLO
7 V
SW Pin
Inductor
Current
Vin
t2
I
LIM
V
CC
V
IN
t1
t3
I
O
0V
V
OUT
SM72485
SNVS697D –JANUARY 2011–REVISED APRIL 2013 www.ti.com
The turn-on sequence is shown in Figure 10. During the initial delay (t1) VCC ramps up at a rate determined by
its current limit and C3 while internal circuitry stabilizes. When V
CC
reaches the upper threshold of its under-
voltage lock-out (UVLO, typically 5.3V) the buckswitch is enabled. The inductor current increases to the current
limit threshold (I
LIM
) and during t2 V
OUT
increases as the output capacitor charges up. When V
OUT
reaches the
intended voltage the average inductor current decreases (t3) to the nominal load current (I
O
).
Figure 10. Startup Sequence
Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5V reference. In normal operation (the output voltage is
regulated), an on-time period is initiated when the voltage at FB falls below 2.5V. The buck switch will stay on for
the on-time, causing the FB voltage to rise above 2.5V. After the on-time period, the buck switch will stay off until
the FB voltage again falls below 2.5V. During start-up, the FB voltage will be below 2.5V at the end of each on-
time, resulting in the minimum off-time of 300 ns. Bias current at the FB pin is nominally 100 nA.
Over-Voltage Comparator
The feedback voltage at FB is compared to an internal 2.875V reference. If the voltage at FB rises above 2.875V
the on-time pulse is immediately terminated. This condition can occur if the input voltage, or the output load,
change suddenly. The buck switch will not turn on again until the voltage at FB falls below 2.5V.
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