Datasheet
SM72480
SNIS156C –NOVEMBER 2010–REVISED APRIL 2013
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for +V
DD
= +1.6V to +5.5V. Boldface limits apply for T
A
= T
J
= T
MIN
to
T
MAX
; all other limits T
A
= T
J
= 25°C.
Units
Symbol Parameter Conditions Typical
(1)
Limits
(2)
(Limit)
OVERTEMP DIGITAL OUTPUT ACTIVE LOW, OPEN DRAIN
T
A
= 30 °C 0.001
Logic "1" Output Leakage
I
OH
1 μA (max)
Current
(3)
T
A
= 150 °C 0.025
V
TEMP
ANALOG TEMPERATURE SENSOR OUTPUT
V
TEMP
Sensor Gain Trip Point = 105°C -7.7 mV/°C
Trip Point = 125°C or 120°C −10.3 mV/°C
Source ≤ 90 μA
−0.1 −1 mV (max)
(V
DD
− V
TEMP
) ≥ 200 mV
1.6V ≤ V
DD
< 1.8V
Sink ≤ 100 μA
0.1 1 mV (max)
V
TEMP
≥ 260 mV
V
TEMP
Load Regulation
(4)
Source ≤ 120 μA
−0.1 −1 mV (max)
(V
DD
− V
TEMP
) ≥ 200 mV
V
DD
≥ 1.8V
Sink ≤ 200 μA
0.1 1 mV (max)
V
TEMP
≥ 260 mV
Source or Sink = 100 μA 1 Ohm
0.29 mV
V
DD
Supply- to-V
TEMP
V
DD
= +1.6V to +5.5V 74 μV/V
DC Line Regulation
(5)
−82 dB
V
TEMP
Output Load
C
L
Without series resistor. See CAPACITIVE LOADS. 1100 pF (max)
Capacitance
TRIP TEST DIGITAL INPUT
V
IH
Logic "1" Threshold Voltage V
DD
− 0.5 V (min)
V
IL
Logic "0" Threshold Voltage 0.5 V (max)
I
IH
Logic "1" Input Current 1.5 2.5 μA (max)
I
IL
Logic "0" Input Current
(3)
0.001 1 μA (max)
TIMING
Time from Power On to Digital
t
EN
Output Enabled. See definition 1.1 2.3 ms (max)
below.
Time from Power On to Analog V
TEMP
C
L
= 0 pF to 1100 pF
t
V
Temperature Valid. See 1.0 2.9 ms (max)
definition below.
(3) The 1 µA limit is based on a testing limitation and does not reflect the actual performance of the part. Expect to see a doubling of the
current for every 15°C increase in temperature. For example, the 1 nA typical current at 25°C would increase to 16 nA at 85°C.
(4) Source currents are flowing out of the SM72480. Sink currents are flowing into the SM72480.
(5) Line regulation (DC) is calculated by subtracting the output voltage at the highest supply voltage from the output voltage at the lowest
supply voltage. The typical DC line regulation specification does not include the output voltage shift discussed in VOLTAGE SHIFT.
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