Car Stereo System - Car Radio Digital Signal Processor User Manual
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1 Features
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Parameters
• Controlled Baseline
• Endianess: Little Endian, Big Endian
– One Assembly Site
– Test Site
• 64 Bit External Memory Interface (EMIFA)
– One Fabrication Site
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
• Enhanced Diminishing Manufacturing Sources
Synchronous Memories (SBSRAM, ZBT
(DMS) Support
SRAM)
• Enhanced Product-Change Notification
– Supports Interface to Standard Sync
• Qualification Pedigree
(1)
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)
• High-Performance Fixed-Point DSP (C6455)
– 32M Byte Total Addressable External
– 1.39 ns, 1.17 ns, 1 ns, and 0.83 ns
Memory Space
Instruction Cycle Time
• Four 1x Serial RapidIO® Links (or One 4x),
– 1 GHz Clock Rate
v1.2 Compliant
– Eight 32 Bit Instructions/Cycle
– 1.25/2.5/3.125 Gbps Link Rates
– 9600 MIPS/MMACS (16 Bits)
– Message Passing, DirectIO Support, Error
– Commercial Temperature (0 ° C to 90 ° C)
Management Extensions, and Congestion
– Extended Temperature (–40 ° C to 105 ° C)
Control
– S-Temp (–55 ° C to 105 ° C)
– IEEE 1149.6 Compliant I/Os
• C64x+™ DSP Core
• DDR2 Memory Controller
– Dedicated SPLOOP Instruction
– Interfaces to DDR2-533 SDRAM
– Compact Instructions (16 Bit)
– 32 Bit/16 Bit, 533 MHz (data rate) Bus
– Instruction Set Enhancements
– 512M Byte Total Addressable External
– Exception Handling
Memory Space
• C64x+ Megamodule L1/L2 Memory
• EDMA3 Controller (64 Independent Channels)
Architecture:
• 32/16 Bit Host-Port Interface (HPI)
– 256K Bit (32K Byte) L1P Program Cache
• 32 Bit 33/66 MHz, 3.3 V Peripheral Component
(Direct Mapped)
Interconnect (PCI) Master/Slave Interface
– 256K Bit (32K Byte) L1D Data Cache
Conforms to PCI Local Bus Specification
[2-Way Set-Associative]
(version 2.3)
– 16M Bit (2096K Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation)
• One Inter-Integrated Circuit (I
2
C) Bus
– 256K Bit (32K Byte) L2 ROM
• Two McBSPs
– Time Stamp Counter
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
• Enhanced VCP2
– IEEE 802.3 Compliant
– Supports Over 694 7.95 Kbps AMR
– Supports Multiple Media Independent
– Programmable Code Parameters
Interfaces (MII, GMII, RMII, and RGMII)
– Eight Independent Transmit (TX) and
• Enhanced Turbo Decoder Coprocessor (TCP2)
Eight Independent Receive (RX) Channels
– Supports up to Eight 2 Mbps 3GPP
(6 Iterations)
• Two 64 Bit General-Purpose Timers,
– Programmable Turbo Code and Decoding Configurable as Four 32 Bit Timers
• UTOPIA
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
– UTOPIA Level 2 Slave ATM Controller
extended temperature range. This includes, but is not limited
– 8 Bit Transmit and Receive Operations up
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
to 50 MHz per Direction
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
– User-Defined Cell Format up to 64 Bytes
life. Such qualification testing should not be viewed as
• 16 General-Purpose I/O (GPIO) Pins
justifying use of this component beyond specified
performance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C64x+, JTAG, C64x+, VelociTI, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.