Car Stereo System - Car Radio Digital Signal Processor User Manual

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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NAME NO.
RAPIDIO SERIAL PORT
RIOCLK AF15 I RapidIO serial port source (reference) clock
RIOCLK AG15 I Negative RapidIO serial port source (reference) clock
RIOTX3 AF17
RIOTX2 AG18
O/Z RapidIO transmit data bus bits [3:0] (differential)
RIOTX1 AG22
RIOTX0 AF23
RIOTX3 AF18
RIOTX2 AG19
O/Z RapidIO negative transmit data bus bits [3:0] (differential)
RIOTX1 AG21
RIOTX0 AF22
RIORX3 AH18
RIORX2 AJ18
I RapidIO receive data bus bits [3:0] (differential)
RIORX1 AJ22
RIORX0 AH22
RIORX3 AH17
RIORX2 AJ19
I RapidIO negative receive data bus bits [3:0] (differential)
RIORX1 AJ21
RIORX0 AH23
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR MII/RMII/GMII
UTOPIA transmit address pin (UXADDR4) ( I) 4 or MDIO serial clock (MDCLK)
UXADDR4/MDCLK M5 I/O/Z IPD
for MII/RMII/RGMII mode ( O)
UTOPIA transmit address pin 3 (UXADDR3) ( I) or MDIO serial data (MDIO) for
UXADDR3/MDIO N3 I/O/Z IPU
MII/RMII/RGMII mode ( I/O)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR RGMII
RGMDCLK B4 O/Z MDIO serial clock (RGMII mode) (RGMDCLK) ( O)
RGMDIO A4 I/O/Z MDIO serial data (RGMII mode) (RGMDIO) ( I/O)
ETHERNET MAC (EMAC) [MII/RMII/GMII]
If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configuration pins —
the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC/MDIO interface.
For more detailed information on the EMAC configuration pins, see Section 3 , Device Configuration.
UTOPIA receive clock (URCLK) driven by Master ATM Controller ( I) or when
the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is
URCLK/MRCLK H1 I
EMAC receive clock (MRCLK) for MII [default] or GMII. MACSEL[1:0]
dependent.
UTOPIA receive cell available status output signal from UTOPIA Slave ( O) or
URCLAV/MCRS/ when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
J4 I/O/Z
RMCRSDV pin is EMAC carrier sense (MCRS) ( I) for MII [default] or GMII, or EMAC carrier
sense/receive data valid (RMCRSDV) ( I) for RMII. MACSEL[1:0] dependent.
UTOPIA receive Start-of-Cell signal ( I) or when the UTOPIA peripheral is
URSOC/MRXER/
H4 I disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is EMAC receive error
RMRXER
(MRXIR) ( I) for MII [default], RMII, or GMII. MACSEL[1:0] dependent.
UTOPIA receive interface enable input signal ( I). Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
URENB/MRXDV H5 I
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid (MRXDV) ( I). MACSEL[1:0]
dependent.
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