Car Stereo System - Car Radio Digital Signal Processor User Manual

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Revision History
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS276G device-specific
data sheet to make it an SPRS276H revision.
Scope: Applicable updates to the C64x device family, specifically relating to the SM320C6455-EP device,
have been incorporated.
C6455 Revision History
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Global Added 1.2-GHz device information
Section 1 Features:
Added 0.83-ns instruction cycle time
Added 1.2-GHz clock rate
Section 2.1 Device Characteristics:
Table 2-1 , Characteristics of the C6455 Processor:
Added 1200 (1.2 GHz) Frequency
Added 0.83 ns (C6455-1200) [1.2-GHz CPU] Cycle Time
Added -1200 device to 1.25-V Core Voltage
Section 2.8.2 Device Support:
Added Device Speed Range 2 = 1.2 GHz to Figure 2-13 , C64x+™ DSP Device Nomenclature (including the
SM320C6455-EP DSP)
Section 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature
Added a row to P
CDD
Core supply power for CPU frequency = 1200 MHz with a TYP value of 1.79 W
Added a row to P
DDD
I/O supply power for CPU frequency = 1200 MHz with a TYP value of 0.54 W
Section 7 C64x+ Peripheral Information and Electrical Specifications:
Added -1200 to all timing and switching characteristics tables
Section 7.7.1 PLL1 Controller Device-Specific Information:
Changed third paragraph to ... PLLOUT is set to 1200 MHz ...
Changed PLLOUT MAX value to 1200 MHz in Table 7-16 , PLL1 Clock Frequency Ranges
Section 7.8 PLL2 and PLL2 Controller:
Changed C162 value to 0.1 µ F in Figure 7-23 , PLL2 Block Diagram
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