Car Stereo System - Car Radio Digital Signal Processor User Manual

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7.19.3 UTOPIA Electrical Data/Timing
UXCLK
1
2
3
4
4
URCLK
1
2
3
4
4
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-106. Timing Requirements for UXCLK
(1)
(see Figure 7-74 )
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
1 t
c(UXCK)
Cycle time, UXCLK 20 ns
2 t
w(UXCKH)
Pulse duration, UXCLK high 0.4t
c(UXCK)
0.6t
c(UXCK)
ns
3 t
w(UXCKL)
Pulse duration, UXCLK low 0.4t
c(UXCK)
0.6t
c(UXCK)
ns
4 t
t(UXCK)
Transition time, UXCLK 2 ns
(1) The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
Figure 7-74. UXCLK Timing
Table 7-107. Timing Requirements for URCLK
(1)
(see Figure 7-75 )
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
1 t
c(URCK)
Cycle time, URCLK 20 ns
2 t
w(URCKH)
Pulse duration, URCLK high 0.4t
c(URCK)
0.6t
c(URCK)
ns
3 t
w(URCKL)
Pulse duration, URCLK low 0.4t
c(URCK)
0.6t
c(URCK)
ns
4 t
t(URCK)
Transition time, URCLK 2 ns
(1) The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
Figure 7-75. URCLK Timing
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