Car Stereo System - Car Radio Digital Signal Processor User Manual

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RMREFCLK
(Input)
1
2
3
3
4
5
MRXD1-MRXD0,
MCRSDV,
MRXER (Inputs)
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps
(1)
(see Figure 7-67 )
-720
-850
A-1000/-1000
NO. UNIT
-1200
MIN MAX
Setup time, receive selected signals valid before MREFCLK (at DSP)
1 t
su(MRXD-MREFCLK)
4.0 ns
high/low
2 t
h(MREFCLK-MRXD)
Hold time, receive selected signals valid after MREFCLK (at DSP) high/low 2.0 ns
(1) For RMII, receive selected signals include: MRXD[1:0], MRXER, and MCRSDV.
Figure 7-67. EMAC Receive Interface Timing [RMII Operation]
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